A low-latency dual-mode lockstep-tolerant soft error handler system

A processor system, soft error technology, applied in the directions of non-redundant fault handling, response error generation, etc., can solve the problems of large delay time of the processor system, not considering soft errors, low accuracy, etc., to improve The effect of universality, reduced time overhead, and low latency

Active Publication Date: 2021-05-28
JIANGNAN UNIV
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Problems solved by technology

[0004] The existing dual-mode lockstep soft error processor system generally only considers the soft errors that occur during normal execution, and does not consider the soft errors that occur during the establishment of checkpoints and fault recovery
In addition, the existing processor-oriented dual-mode lockstep fault-tolerant technology generally adopts a fixed-interval checkpoint algorithm or a dynamic checkpoint algorithm based on soft error rate. These algorithms have low accuracy in predicting soft error distribution, and In the case of unknown and complex soft error distribution, these schemes will introduce a large delay time to the processor system

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  • A low-latency dual-mode lockstep-tolerant soft error handler system
  • A low-latency dual-mode lockstep-tolerant soft error handler system
  • A low-latency dual-mode lockstep-tolerant soft error handler system

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Embodiment 1

[0097] This embodiment provides a low-latency dual-mode lockstep soft error-tolerant processor system. For the hardware architecture diagram, see figure 1 , the system includes: memory, two identical processors CPU0 and CPU1, DMA, bus monitor, synchronous controller, signal comparator and interrupt controller; the system realizes the instruction level parallelism of dual processors, to The two processors CPU0 and CPU1 perform a bit-level comparison for soft error detection.

[0098] The low-latency dual-mode lockstep-tolerant soft error handler system has three sub-functions:

[0099] 1. Soft error detection function: Through the bus controller and the synchronization controller, the processors CPU0 and CPU1 realize instruction-level parallelism, and then perform bit-level comparison of the two processors CPU0 and CPU1 through the signal comparator to realize lockstep Soft error detection for processor systems;

[0100] 2. Pervasive checkpoint and rollback recovery: The perv...

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Abstract

The invention discloses a low-delay dual-mode lockstep soft error tolerance processor system, which belongs to the technical field of processor error tolerance. The system realizes the detection of soft errors in the processor system through a dual-mode lockstep architecture; by adopting a universal checkpoint and rollback recovery algorithm, the system can cope with a variety of soft errors and improve the reliability of the fault recovery method Universality: The system adopts an adaptive dynamic checkpoint method, predicts the next soft error interval with the soft error interval history table SEIHT and the pattern history table PHT, and increases or decreases the setting frequency of the checkpoint according to the prediction result , this method considers the long-term and short-term characteristics of soft error history at the same time, effectively reduces the average execution time of processor tasks, and solves the problem of large delay time introduced by the current dual-mode lockstep fault-tolerant technology for processors.

Description

technical field [0001] The invention relates to a low-delay dual-mode lockstep soft error tolerance processor system, which belongs to the technical field of processor error tolerance. Background technique [0002] Processor-oriented dual-mode lockstep (lockstep) technology is a micro-architecture-level soft error detection technology, which can be combined with fault recovery technology to implement a soft error-tolerant processor system, which can effectively improve processor performance. reliability. [0003] Compared with fault-tolerant technologies at other levels such as processes, devices, and software, micro-architecture-level fault-tolerant technologies have the characteristics of not needing to pay attention to the underlying design, strong versatility, and easy to implement, and are widely used in safety-critical fields such as aerospace. Compared with the traditional multi-mode redundancy technology, the dual-mode fault-tolerant architecture based on dual-proce...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/07
CPCG06F11/0793
Inventor 虞致国常龙鑫顾晓峰
Owner JIANGNAN UNIV
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