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In-loop dual backup system

A dual backup and system bus technology, applied in the field of integrated circuits, can solve the problems of lower core processor performance and high complexity, and achieve the effect of reducing the risk of common cause failure and improving the fault diagnosis rate

Active Publication Date: 2020-11-13
NANJING SEMIDRIVE TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

With the above form, the complexity of verifying the correctness of the external memory content and the content copy process is very high, which reduces the performance of the core processor

Method used

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  • In-loop dual backup system
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  • In-loop dual backup system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] figure 2 It is a schematic structural diagram of an in-ring dual backup system according to Embodiment 1 of the present invention, as figure 2 As shown, the in-ring dual backup system of the present invention includes a first peripheral device controller 101, a second peripheral device controller 102, a first synchronizer 103, a second synchronizer 104, a first peripheral device 105, a second peripheral device 106, and response detector 111, where,

[0035] The first peripheral device controller 101, which receives the operation command to the first peripheral device 105 from the system bus, and parses the operation command into a control signal and sends it to the first peripheral device 105; receives the first peripheral device from the response detector 111 105 is the response result of execution according to the instruction of the control signal.

[0036] The second peripheral device controller 102, which delays the received operation command to the first periph...

Embodiment 2

[0044] image 3 It is a schematic structural diagram of an in-ring dual backup system according to Embodiment 2 of the present invention, as shown in image 3 As shown, the in-ring dual backup system of the present invention includes a first peripheral device controller 101, a second peripheral device controller 102, a first synchronizer 103, a second synchronizer 104, a first peripheral device 105, a second Peripheral device 106, first comparator 107, second comparator 108, third comparator 109, distributor 110, and response detector 111, wherein,

[0045]The first peripheral device controller 101, which receives the operation command to the first peripheral device 105 from the system bus, and resolves the operation command as a control signal and sends it to the first peripheral device 105 and the third comparator 109; from the distributor 110 A response result of execution according to the instruction of the control signal of the first peripheral device 105 is received.

...

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Abstract

The invention discloses an in-loop dual-backup system. Two peripheral device controllers and two peripheral device structures are adopted; the two peripheral device controllers work in a dual-core lock step mode; the peripheral devices are respectively controlled by different peripheral device controllers; and one of the peripheral devices negates the written data according to bits. According to the in-loop dual-backup system, the dual-backup peripheral device is seamlessly connected to the loop of the dual-core lockstep peripheral device controller, so that the fault diagnosis rate of peripheral device access is greatly improved, and meanwhile, due to the isomerism of data stored in the peripheral device, the risk of common cause failure is greatly reduced.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an in-ring dual backup system. Background technique [0002] In the application scenario of a high-security vehicle electronic system, the program and data of the core processor are often stored inside the processor, and there are few solutions for expanding the external memory outside the core processor. The main reason is the lack of a safe and effective core processor external expansion memory solution. [0003] With the increasing complexity of the functions of the vehicle electronic system, its core processor has more and more requirements for program and data storage space. Under this trend, the storage space inside the processor is becoming more and more tight. In the case of insufficient internal storage space, external storage is required. Whether or not a safe peripheral memory expansion scheme can be found becomes the key to solving this problem. [000...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/14
CPCG06F11/1448
Inventor 张力航仇雨菁
Owner NANJING SEMIDRIVE TECH CO LTD
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