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Allocation of cache memory data section and initial mechanism

A technology of initialization and initialization instructions, which is applied in the field of microelectronics and can solve problems such as prefetch instructions cannot operate

Inactive Publication Date: 2004-04-07
IP FIRST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But prefetch instructions don't work on operands in the program flow

Method used

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  • Allocation of cache memory data section and initial mechanism
  • Allocation of cache memory data section and initial mechanism
  • Allocation of cache memory data section and initial mechanism

Examples

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Embodiment Construction

[0099] The following description, provided in the context of a specific embodiment and its prerequisites, will enable one of ordinary skill in the art to utilize the invention. However, various modifications to this preferred embodiment will be readily apparent to those skilled in the art, and the general principles discussed herein can be applied to other embodiments as well. Therefore, the present invention is not limited to the specific embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0100] Given the previous background discussion of how today's pipelined microprocessors perform prefetch operations, in light of the figure 1 To 3, an example will be presented that highlights the limitations of today's prefetching techniques. Immediately afterwards, at Figures 4 to 18 , will present a discussion of the invention. The present invention enables the programmer to command the ...

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Abstract

A microprocessor apparatus is provided that enables exclusive prefetch and initialization of a block of cache lines from memory. The apparatus includes translation logic and execution logic. The translation logic translates a block allocate and initialize instruction into a micro instruction sequence that directs a microprocessor to prefetch a block of cache lines in an exclusive state and to initialize the block of cache lines to a specified value. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the block of cache lines in the exclusive state. Upon receipt, the execution logic initializes the block of cache lines to the specified value.

Description

technical field [0001] The present invention relates to the field of microelectronics, and in particular to an apparatus and method that enable a programmer to instruct a microprocessor to perform configuration and initialization of a block cache line on its internal cache (cache) ) prefetch operation (prefetch operation). Background technique [0002] US application case number filing date Docket (DOCKET) Number (NUMBER) patent name 10 / 364911 2 / 11 / 2003 CNTR.2157 prefetcher with intent to store system 10 / 364920 2 / 11 / 2003 CNTR.2162 Cache line configuration and initialization Device and method 10 / 364919 2 / 11 / 2003 CNTR.2182 The purpose of segment memory is to store Prefetch Mechanism [0003] In today's microprocessors, the data transfer speed between its internal logic blocks far exceeds its access speed with external memory. In an x86 deskto...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/00G06F9/22G06F9/30G06F9/318G06F9/34G06F9/38G06F12/00G06F12/08
CPCG06F12/0831G06F9/30047G06F12/0862G06F2212/6028G06F9/3017
Inventor 罗德尼·E·胡克
Owner IP FIRST
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