113results about How to "Increase data bandwidth" patented technology

A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.

The invention discloses a VPX parallel DSP (Digital Signal Processing) board card based on SoC (System on a Chip) online reconstruction. An FPGA (Field Programmable Gate Array) chip is used as a board stage SoC controller; and two DSP chips are used as core operation chips of a DSP board card. During the practical configuration of the DSP chips, the FPGA chip used as the SoC controller can complete the dynamic re-configuration of work code by GE (Gigabit Ethernet) through the hardware resetting on the DSP and the switching on the starting mode; and the flexibility and the real-time performance during the DSP are greatly improved. The DSP chips receive two kinds of high-speed serial bus signals of SRIO (Serial Rapid Input Output) X4 and the GE transmitted through a VPX interface, repacking the transferred PCIE (Peripheral Component Interface Express) X2 high-speed serial bus signal through a PCIE exchange chip, and receives a data signal to be processed and a control instruction; or the DSP chips receive the GE protocol signal of a peripheral component through an RJ45 net port.

The invention discloses a Flash based PCIE (peripheral component interface express) board for data storage. The board is characterized in that an FPGA chip is used as the master control module, DDR memories are connected to serve as buffer modules and Flash chips are simultaneously connected to serve as storage modules; a PCIE controller, a DDR controller, a command parser, soft Cache hit logics,an X-Card management module, ECC check data logics, Flash block address mapping, an arbiter and a Flash controller are implemented inside FPGA and complete respective functions by downloading the programs to the FPGA. The communication interface adopts the PCIE interface which has high data transmission rate. PCI-E also supports advanced power management, hot plug and synchronous data transmission and optimizes the bandwidth for the preferentially transmitted data.

An electronic data transport system includes a mobile access point and a carrier for moving the mobile access point over a surface and/or water route. The mobile access point includes a communications module for wirelessly transmitting data to and receiving data from one or more client devices when the client device is in proximity to the mobile access point.

In certain embodiments, a wireless communication link includes a wireless receiver that receives a circular polarized signal from a remotely configured transmitter. The circular polarized signal has a polarization vector that rotates at a radial velocity. The wireless receiver determines a phase deviation in the radial velocity of the polarization vector and demodulates information from the circular polarized signal according to the determined phase deviation. The phase deviation is caused by a frequency deviation of the circular polarized signal generated by the transmitter.

The present invention is to contribute to reduction in cost of a system performing image recognition and display control on input image data. A data processor includes a central processing unit, a graphic controller, a display controller, an image recognizing module, a memory controller capable of controlling an access to an external memory, and image data input units for inputting image data from the outside and capable of performing necessary format conversion, and the components are formed on a single semiconductor substrate. The display controller performs display control on the image data read from the external memory via the memory controller. The image data input unit stores the image data input from the outside or the image data subjected to the necessary format conversion into a first area in the external memory via the memory controller. The image recognizing module or central processing unit executes an image process using the image data in the first area or image data in a second area, obtained by performing necessary data process on the image data, and stores a result of the process in a third area in the external memory.

A portable electronic device comprises a first wireless interface and a second wireless interface. The first wireless interface is controlled to perform a control signaling with a further device over the first wireless interface. The second wireless interface is selectively activated to transmit data traffic to the further device and/or to receive the data traffic from the further device over the second wireless interface. The first wireless interface is maintained in an activated state to control the data traffic over the second wireless interface by the control signaling over the first wireless interface while the second wireless interface is activated.

The invention provides a memory controller based on the burst disorder memory access dispatching, which is used to the burst disorder memory access dispatching accessed by a memory, and comprises a reading-writing queue module for storing the reading-writing memory access from a processor in a two-dimension mode, a block arbitration module for arbitrating a burst memory access from each block in each memory clock period, and an event selection module for selecting the final memory access operation from the burst of each block after arbitrated to send to the memory. The block is conducted with the burst arbitration to dispatch the disorder memory access through changing the structure of a queue and adopting the priority expression provided by the invention, thereby increasing the data bandwidth of the memory, and reducing the executing time of the processor.

A centralized router based on PCI Express bus as its internal bus for wide bandwidth features that such units in the router as root multiplexer, PCI Express switch and interfaces are connected via PCI Express bus for data transmission.

The invention belongs to the technical field of real-time adaptive signal processing, particularly relates to an FPGA implementation device and method of an FBLMS algorithm based on a block floating point, and aims to solve the problem that conflicts exist among performance, speed and resources when an existing FPGA device implements the FBLMS algorithm. The method comprises the following steps that an input cache transformation module performs block cache recombination on a reference signal, converts the reference signal into block floating points and then performs FFT transformation; a filtering module carries out filtering in a frequency domain and carries out dynamic bit cutting; an error calculation and output caching module performs block caching on the target signal, subtracts the filtered output after the target signal is converted into a block floating point, and converts the result into a fixed-point system to obtain a final cancellation result; and a weight adjustment calculation module and a weight update storage module obtain the adjustment amount of the weight and update the weight block by block. Aiming at a recursive structure of the FBLMS algorithm, a block floating point data format and a dynamic bit cutting method are adopted, so the data is ensured to have a large dynamic range and high precision, conflicts among performance, speed and resources are solved,and the reusability and expansibility are also improved through modular design.

An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven with the small voltage swing, which is generated by small swing circuits. The integrated circuit further includes regeneration circuits, which are receiving small voltage swing inputs and are outputting first, or full voltage swings. The application of the small voltage swing to the signal lines saves power in the integrated circuit. A wide bandwidth, full-wordline I/O, memory integrated circuit has simultaneously operable connection paths between essentially all the memory cells that are attached to the same wordline and the corresponding I/O terminals, and it has a single ended data-line structure.

The invention discloses a BCH (Broadcast Channel) encoding and decoding method and a device. The BCH encoding method comprises the following steps of: setting a lookup table; pre-storing all levels of coefficient of a residue polynomial in the lookup table; and combining the lookup table to obtain a state of an encoding state register at the next moment according to the state of the encoding state register at the present moment and 8-bit data to be encoded. Meanwhile, the embodiment of the invention also provides a BCH decoding method, comprising the following steps of: reading data of all verification sections of a page redundancy area in a flash memory and storing the data into a data cache; reading the data of a plurality of information sections of a page information area in the flash memory; determining the position of each error according to the corresponding accompany type of the data in each information section and storing the positions of the errors into the data cache; and finishing error correction by a data reading part of an on-chip system according to the error information in the data cache. The BCH encoding and decoding method and the device are suitable for the BCH encoding and decoding of the flash memory application facing to the on-chip system.

The invention relates to a communication device on the basis of a power line and a GPRS (General Packet Radio Service), which is characterized by comprising a communication head end, a communication terminal and a GPRS wireless terminal, wherein the communication head end is communicated with the GPRS wireless terminal through a first serial interface; and the communication head end carries out Ethernet communication with the communication terminal through the power line. The GPRS wireless terminal, the communication head end and the communication terminal are combined to form a complete remote wireless multipoint Ethernet transmission control platform. The communication device has the characteristics of large data bandwidth and high transmission reliability, so that the communication device is suitable for application to monitoring various power networks or industrial control and the like.

The invention discloses a high-power high-stability variable-load high-frequency acceleration system. The high-power high-stability variable-load high-frequency acceleration system comprises a low-level high-frequency controller, a power amplification and transmission system and a high-frequency cavity; the power amplification and transmission system comprises a high-frequency machine, a transmission line and a coupling window; the low-level high-frequency controller is responsible for generating low-level high-frequency signals with appropriate values, and driving the high-frequency machine by the generated low-level high-frequency signals; the high-frequency machine is responsible for amplifying the low-power high-frequency signals into high-power high-frequency electromagnetic waves, and then transmitting the electromagnetic waves to the coupling window through the transmission line; the coupling window is used for coupling high-frequency power from the amplification system to the high-frequency cavity, and is characterized in that the coupling window is a dynamic adjustable coupling window; the high-frequency cavity is of a runway cavity structure; the invention further discloses an automatic adjustment coupling degree algorithm of the high-power high-stability variable-load high-frequency acceleration system, wherein the algorithm comprises the steps that a dynamic reflection power adjustment coupling degree algorithm is initialized; and the final calculation formula of the dynamic reflection power adjustment coupling degree is obtained.

A flash memory card used for differential data transmission comprises a differential data path which can be used for communication between the flash memory card and a host device, a differential signal is used for execution, the differential data path can be used for translation between differential signals and specific storage card signals so as to control reading/writing-in operations of a memory bank array of the flash memory card, the specific memory card signals can be signals of standard multimedia memory cards, safety digital memory cards, memory stick memory cards or compact flash memory cards and the like, the host device can contain a similar differential data path so as to provide the differential data transmission capability; and the differential data transmission is utilized instead of non-known clock data transmission, so that the integral data bandwidth between the flash memory card and the host device can be greatly increased, and the energy consumption and pin demands can be reduced.