4results about How to "Increase data bandwidth" patented technology

The present application discloses a multi-die storage and computing architecture FPGA with high storage bandwidth, and relates to the field of FPGA technology. The multi-die storage and computing architecture FPGA encapsulates an FPGA die and a storage die together, and a storage and computing unit is formed inside the FPGA die. Each storage and computing unit performs calculations based on instructions and data of a local storage unit. The data read and write ports of the local storage unit in each storage and computing unit are connected to a silicon connection layer, and are connected to the data read and write ports of the storage die via cross-die connections in the silicon connection layer to form a storage and computing read and write channel. The storage die reads and writes data to the connected local storage unit through the storage and computing read and write channel, and a larger data bandwidth can be achieved, so that the waiting time for data can be reduced when multi-core parallel storage and computing operations are realized through multiple storage and computing units, and the storage and computing performance is excellent, the data processing efficiency is high, and the computing speed is fast.

The utility model relates to filter protection circuit and camera of camera head, including image acquisition sensor, connecting port and image processing chip, still including TF common mode filter circuit, electrostatic protection circuit and spread spectrum IC circuit, TF common mode filter circuit is connected with image acquisition sensor, electrostatic protection circuit and TF common mode filter circuit and connecting port are connected, and the CSI the CLK port of image processing chip, the MCLK port of connecting port all are connected with spread spectrum IC circuit, application circuit of this application can reduce the common mode noise of data to the greatest extent, reduce EMI radiation, can reduce electrostatic interference data transmission, can also make the synchronous clock of protocol also have spread spectrum, thereby reducing clock radiation, this application can solve the EMI radiation emission and electrostatic protection problem of MIPI CSI -2 camera head very well, especially applicable to small, data bandwidth is high, clock frequency is high and the camera product of transmission MIPI CSI -2 protocol.

According to the remote communication interaction link system of the electric power inspection unmanned aerial vehicle, a data link solution which is high in reliability, good in safety, high in integration level and long in transmission distance is provided based on the structure and mechanism of a UAV data link. The design and construction of a power inspection UAV data link system hardware scheme are completed, data link system hardware equipment suitable for a power inspection UAV system is designed, the characteristics, the configuration mode and the installation mode of the data link system hardware equipment are described in detail, and an anti-interference design is provided for a power UAV control panel. A whole set of communication protocol is designed according to an unmanned aerial vehicle data link system, data congestion is demonstrated, data traffic is reasonably arranged through design and calculation, and generation of data congestion is prevented. All parameter indexes of the limit communication distance of the system are defined, and the data link design scheme is high in reliability, good in safety, high in integration level and long in transmission distance.

The present application discloses an instruction scheduling device and method. The instruction scheduling device is used in a controller of a storage device. The controller is coupled to multiple flash memory chips through a first channel. The instruction scheduling device includes: an instruction cache unit, which caches various instructions adapted to multiple flash memory chips through multiple instruction queues; a remaining time calculation unit, which is used to calculate the remaining execution time of a DQ instruction that is currently transmitting data through a data bus of the first channel; an arbitration unit, which is used to take instructions from multiple instruction queues, compare the estimated execution time of one or more CA instructions with the remaining execution time, so as to determine a CA instruction that is preferentially executed by the CA execution unit. The device improves the probability of CA instructions and DQ instructions being executed in parallel by optimizing the behavior of CA instructions and DQ instructions being executed in parallel under the SCA interface, so that the DQ bus obtains higher utilization and higher data bandwidth.