97 results about "Regenerative circuit" patented technology

A non-volatile static random access memory cell and includes a bistable regenerative circuit coupled to first and second transistors and to first and second non-volatile memory cells. Methods of use include directly transferring a complementary data bit between the non-volatile memory cell and the bistable regenerative circuit. Alternatively, complementary data from the bistable regenerative circuit may be regenerated by a sense amplifier and a second bistable regenerative circuit before being transferred to non-volatile memory cells in a column of memory cells. The bistable regenerative circuit may be reset to ground potential. Applications using the non-volatile SRAM cell with direct read out from the bistable regenerative circuit include a non-volatile flip-flop or non-volatile multiplexer.

Disclosed is a data regeneration circuit including a decision gate for regenerating a symbol stream (e.g., bit stream) by comparing the amplitude of individual symbols thereof to a decision threshold and outputting a logic level in accordance with each comparison. Threshold optimization circuitry dynamically measures first and second probability distribution points of each symbol, and based on the measurements, optimizes the decision threshold applied to the decision gate. A parallel pseudoerror path including a pseudoerror decision gate and pseudoerror counter may be employed to facilitate the measurements.

The invention discloses an automotive energy-regenerative active suspension system with rigidity and damping variable. The suspension system comprises a suspension variable-rigidity mechanism, a suspension energy-regenerative mechanism and an active suspension control system. The suspension variable-rigidity mechanism comprises a low-rigidity spring, a magneto-rheological damper and a high-rigidity spring. The suspension energy-regenerative mechanism is formed by bi-directionally connecting a linear motor, an energy-regenerative circuit and a storage battery in sequence. The active suspension control system includes a controller. The data input end of the controller is connected with a vibration measuring and processing circuit. The magneto-rheological damper and the control input end of the linear motor are respectively connected with the control output end of the controller. The suspension system can automatically adjust the damping and rigidity at the same time, so that the good steering stability and ride comfort of a finished automobile are achieved; the control system is high in response speed; energy consumption is substantially lowered, and therefore the economy requirement of the finished automobile is met; moreover, the structure and a control algorithm are simple, working is stable and reliable, service life is long, and the suspension system can be conveniently applied to an existing automotive suspension so that real-time control can be achieved.

The magnetic bearing control device (1) has a motor drive circuit (13) provided with an inverter (13a) for driving the motor (4) capable of generating an electric power, the inverter being controlled by an inverter control circuit (14), and an over-speed detection circuit (17) for detecting the number of revolutions of the rotor (3) that is being rotated by the motor (4), the rotor being supported in non-contact manner by a magnetic bearing (5). When the over-speed detection circuit (17) detects that the rotor (3) is being rotated at a preset number of revolutions or more, the motor drive circuit (13) performs a switching operation of a switch portion 13c provided in the motor drive circuit (13) to separate the inverter (13a) from the motor (4) and connect the motor (4) to a regenerative circuit (13b), whereby the magnetic bearing (5) is driven and controlled, employing a regenerative electric power of the motor (4).

A power management circuitry for a peripheral electronic device includes a power regeneration circuitry, a power selector, a power switch and an audio signal detection circuitry. The power regeneration circuitry receives a continuous periodic sound wave from an audio device and converts the continuous periodic sound wave into an amplified DC electrical signal. The power source selector receives the amplified DC electrical signal and input from a primary power source and provides a power signal output. The audio signal detection circuitry receives the amplified DC electrical signal and transmits a wake-up signal to the power switch circuitry. The power switch circuitry is turned on by the wake-up signal and connects the power source selector to the peripheral electronic device main circuitry and transfers the power signal output to the peripheral electronic device main circuitry.

A non-volatile memory array includes a plurality of word-lines and a plurality of columns. One of the columns further includes a bistable regenerative circuit coupled to a first, a second, a third, and a fourth signal lines. The column also includes a non-volatile memory cell having current carrying terminals coupled to the first and second signal lines and a control terminal coupled to one of the plurality of word-lines. The column further includes a first transistor and a second transistor. The first transistor is coupled to the first terminal of the bistable regenerative circuit, and to a fifth signal line. The second transistor has a first current carrying terminal coupled to the second terminal of the bistable regenerative circuit, and a second current carrying terminal coupled to a sixth signal line. The gate terminals of the first and second transistors are coupled to a seventh signal line.

According to some preferred embodiments, power converter includes a comparator circuit with feedback from current-fed PI or PID control to select one of two regeneration times of at least one active clamp: i) wherein at low loads a regeneration circuit is turned ON for substantially an entire current-transfer cycle such as to avoid output of current-fed converter continuing to rise; and ii) wherein at high loads the regeneration period is reduced to between about ¼ to ½ of a resonance-frequency cycle so that a resonance between the regeneration capacitance and the transformer's leakage inductance avoids excessive ringing currents and / or lost efficiency.

The magnetic bearing control device (1) has a motor drive circuit (13) provided with an inverter (13a) for driving the motor (4) capable of generating an electric power, the inverter being controlled by an inverter control circuit (14), and an over-speed detection circuit (17) for detecting the number of revolutions of the rotor (3) that is being rotated by the motor (4), the rotor being supported in non-contact manner by a magnetic bearing (5). When the over-speed detection circuit (17) detects that the rotor (3) is being rotated at a preset number of revolutions or more, the motor drive circuit (13) performs a switching operation of a switch portion 13c provided in the motor drive circuit (13) to separate the inverter (13a) from the motor (4) and connect the motor (4) to a regenerative circuit (13b), whereby the magnetic bearing (5) is driven and controlled, employing a regenerative electric power of the motor (4).

The invention discloses high-speed high-precision comparator circuit design. According to the design, a first-level regenerative amplifying circuit and a second-level positive feedback latching circuit are included. According to a comparator, by using the regenerative circuit in a first-level pre-amplifying process, the amplitude of a first-level output signal of the comparator reaches a degree capable of being recognized by a second positive feedback latching level in a shorter time, the speed of the comparator is increased, and therefore the comparator can be applied to a high-speed ADC (analog-digital converter). According to the second positive feedback latching level, two inverters are adopted to isolate the first level and the second level of the comparator, gain of the first-level regenerative amplifying circuit is improved, and equivalent input offset voltage of the comparator is lowered. Besides, compared with a second-order dynamic comparator adopted in the ADC, the load driving capability of the comparator is higher, and delay is more insensitive to changing of an input signal difference.

A semi-adaptive voltage scaling method and device for determining minimal supply voltages for digital electronic semiconductor circuitry, e.g., microprocessors, of electronic devices under production testing and “real” operating conditions. The SAVS operates in a closed-loop during a production test phase of the circuitry and in an open-loop mode in an application (operation) phase of the semiconductor circuitry. During production testing, a lowermost level of the supply voltage for the semiconductor circuitry is determined at one single defined temperature at which operating specifications of the circuit are met. The lowermost level is stored in a dedicated electronic memory of the circuitry together with temperature dependent parameters. Afterwards, when the digital electronic circuitry is operated in a “real” application, e.g., a mobile phone, the device and method reads the previously measured and proven data from the memory and regenerates the minimum level of supply voltage for the circuitry, taking into account the actual temperature of the application. As a result, the digital semiconductor circuitry in the “real” application is supplied with a minimum level of supply voltage, whereby specified parameters of the circuitry are met. Thus, a power consumption of the circuitry is advantageously reduced to a minimum.

A regenerative circuit structure is built up by implementing the following steps in particular:an intermediate layer is made on a support core representing the inner profile of the structure;a series of channels regularly distributed around the core is made with the channels opening to face the intermediate layer, each of the channels being provided with a soluble insert;the support core is preheated and the body of the structure is made by thermal spraying under a vacuum;channels are machined in the body from the outside, and said channels are filled by means of soluble inserts;a closure layer is formed to close the channels in the body, and an outer envelope is formed by thermal spraying under a vacuum, after preheating; andall of the soluble inserts and the intermediate layer are eliminated.

A wavelength converter and a wavelength division-multiplexing optical communication apparatus automatically generate clock signals of a specified frequency that match send / receive digital signals and regenerates timing for the send / receive digital signals. The wavelength converter includes: optical / electrical signal converters (2A, 2B) that convert input optical signals into electric digital signals; clock generator circuits (4A, 4B) that automatically identify the transmission mode for digital signals and generate phase-synchronized clocks of a specified frequency that match the signal transmission mode; timing regeneration circuits (6A, 6B) that regenerate clock timing for the digital signals based upon the phase-synchronized clocks from the clock generator circuits; and electric / optical converters (3A, 3B) that convert the digital signals from the timing regeneration circuits into optical signals of a specified wavelength.

In a circuit suppressing jitters without a synchronizing clock signal and an increase of a circuit scale, input data is regenerated by a data regeneration circuit in a broadband, a predetermined signal pattern which generates phase deviations exceeding a predetermined value is detected from the data regenerated by the data regeneration circuit by a pattern detection circuit, a reverse phase deviation signal having reverse phase deviations of phase deviations corresponding to the predetermined signal pattern is generated by a reverse phase deviation generating circuit, and an output signal of the data regeneration circuit is canceled by a phase deviation correcting circuit with the reverse phase deviation signal.

A hydraulic control apparatus for controlling a hydraulic cylinder for an implement selectively mounted to a work vehicle. The apparatus includes a hydraulic power source, a four-position changeover control valve disposed between the hydraulic cylinder and the hydraulic power source, and an operational mechanism for operating the four-position changeover control valve. The four-position changeover control valve has a first position for moving a rod of the hydraulic cylinder in one direction, a second position for stopping the rod of the hydraulic cylinder, a third position for moving the hydraulic cylinder rod at a high speed in the other direction with using a function of a regenerative circuit and a fourth position for moving the hydraulic cylinder rod in the other direction at a standard speed without using the function of the regenerative circuit, in the mentioned order. The operational mechanism includes, along an operational movement path thereof, a rollback position, a neutral position, a rapid dump position and a standard dump position, the rollback position corresponding to the first position, the neutral position corresponding to the second position, the rapid dump position corresponding to the third position, the standard dump position corresponding to the fourth position, respectively.

An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven with the small voltage swing, which is generated by small swing circuits. The integrated circuit further includes regeneration circuits, which are receiving small voltage swing inputs and are outputting first, or full voltage swings. The application of the small voltage swing to the signal lines saves power in the integrated circuit. A wide bandwidth, full-wordline I / O, memory integrated circuit has simultaneously operable connection paths between essentially all the memory cells that are attached to the same wordline and the corresponding I / O terminals, and it has a single ended data-line structure.

A regenerative circuit structure is built up by implementing the following steps in particular:an intermediate layer is made on a support core representing the inner profile of the structure;a series of channels regularly distributed around the core is made with the channels opening to face the intermediate layer, each of the channels being provided with a soluble insert;the support core is preheated and the body of the structure is made by thermal spraying under a vacuum;channels are machined in the body from the outside, and said channels are filled by means of soluble inserts;a closure layer is formed to close the channels in the body, and an outer envelope is formed by thermal spraying under a vacuum, after preheating; andall of the soluble inserts and the intermediate layer are eliminated.

Embodiments of disclosed configurations include a circuit and system for a sense amplifier having a sensing circuit changing an output voltage at an output node based on a time that is defined by the output voltage reaching a threshold voltage level. The sensing circuit changes the output voltage at the output node before the time. In addition, a regeneration circuit amplifies the changed output voltage at the time. The sense amplifier offers sufficient voltage headroom to improve operation speed and power efficiency.

An apparatus and method for regenerating reset and clock signals and a high-speed digital system using the apparatus and method are provided. In the regenerating circuit of the invention, a clock circuit receives an external clock signal and generates there from an internal clock signal, which is forwarded to a plurality of clocked circuits such as, for example, D flip-flops. A reset circuit receives an external reset signal and generates therefrom an internal reset signal, which is forwarded to the clocked circuits to reset the clock circuits. A clock masking circuit masks the internal clock signal for a masking period such that the clocked circuits are not clocked during the masking period. The high-speed digital system of the invention includes a plurality of function blocks coupled on a bus. The reset and clock regenerating circuit of the invention generates internal reset and clock signals from externally applied reset and clock signals.

The present invention inhibits the voltage jump of a source voltage or an output voltage by an approach which is different from a conventional one. A logic circuit allows an H bridge circuit to be shifted among a plurality of states in a specific sequence. A compulsory regenerating circuit is configured to be switched between an enabled state and a disabled state; while being in the enabled state, the current that flows in from a ground line via the H bridge circuit and a motor coil to a power line back-flows to the ground line.

A methor for storage cell read timing evaluation provides read strength information by using a pulsed ring oscillator. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents.

The present invention relates to a method and an arrangement for the automatic compensation of a DC-level for an incoming signal (IN) converted into an electrical form for the decision threshold level of binarizing limiter (3) in a fibre optic receiver. From the input signal (IN) converted to an electrical form, a comparison signal (INT) is subtracted, whereupon the signal is binarized by the signal limiter (3). Out of the binarized signal (S), a data regeneration circuit (6) generates the most probable transmitted signal. Based on the so achieved output signal (UT) and the binarized signal (S), a difference signal (D) is formed in a difference signal former (4). This is integrated in an integrator (5) and fed back to the limiter's (3) input for the comparison signal (INT). In this way, offset voltages are compensated for. At the same time, account is taken of the true pulse quotient of the incoming optical signal (O).

An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven with the small voltage swing, which is generated by small swing circuits. The integrated circuit further includes regeneration circuits, which are receiving small voltage swing inputs and are outputting first, or full voltage swings. The application of the small voltage swing to the signal lines saves power in the integrated circuit. A wide bandwidth, full-wordline I / O, memory integrated circuit has simultaneously operable connection paths between essentially all the memory cells that are attached to the same wordline and the corresponding I / O terminals, and it has a single ended data-line structure.

A non-volatile static random access memory cell and includes a bistable regenerative circuit coupled to first and second transistors and to first and second non-volatile memory cells. Methods of use include directly transferring a complementary data bit between the non-volatile memory cell and the bistable regenerative circuit. Alternatively, complementary data from the bistable regenerative circuit may be regenerated by a sense amplifier and a second bistable regenerative circuit before being transferred to non-volatile memory cells in a column of memory cells. The bistable regenerative circuit may be reset to ground potential. Applications using the non-volatile SRAM cell with direct read out from the bistable regenerative circuit include a non-volatile flip-flop or non-volatile multiplexer.

A BS digital broadcasting receiver which eliminates the uncertainty of an ODU's phase noise-dependent switching point when switching a receiving system. The receiver is provided with a demodulator circuit (6A) having a carrier regenerating circuit (19A) based on demodulation data in a BPSK modulation section, and with a demodulator circuit (6B) having a carrier regenerating circuit (19B) based on demodulation data in each time-division modulation section, wherein, when a lock for carriers regenerated by the carrier regenerating circuit (19A) is maintained and carriers regenerated by the carrier regenerating circuit (19B) is locked, demodulation data, in the BPSK demodulation section and a QPSK demodulation section, output from the demodulator circuit (6A) and 8-PSK-modulated demodulation data output from the demodulator circuit (6B) are selected by a selector (7) for outputting.

A pulsed ring oscillator circuit for storage cell read timing evaluation provides read strength information. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents.

An internal combustion engine controller that drives an electromagnetic load is provided for improving a fault diagnosis precision of the electromagnetic load and stabilizing a high-speed control without influence of noises even if the drive cycle of the electromagnetic load is short. The internal combustion engine controller has high reliability in a fault diagnosis for a circuit to regenerate counter electromotive energy. The internal combustion engine controller comprises a current source or a voltage source for controlling a potential of the diagnosis position in order to ensure a high-precision fault diagnosis even if the drive cycle of the electromagnetic load, such as the fuel injector, in the internal combustion engine is shortened. Diagnosis timing is optimally set or the number of determinations for averaging is increased in order to ensure the high-precision fault diagnosis without being influenced by unexpected disturbance such as noises. In the fault diagnosis of the regeneration circuit into the booster circuit, an input / output voltage or the regeneration current of a driving switching element of the electromagnetic load is detected.

The tries limit counter is used to refuse annoying income call in defined times. It consists of initial call information acquiring circuit, CPU, display unit, black list memory, keyboard input circuit, line switching circuit, automatic off hook circuit, incoming call regenerative circuit, ringing detecting circuit, off hook detecting circuit, incoming call generating control switch, incoming call inquiry switch, black list inquiry switch and phone number deleting switch.

An apparatus and related method include a voltage-mode biasing network for receiving a reference current and outputting a biasing voltage, and an oscillator core for receiving the biasing voltage and sustaining an oscillation, wherein the voltage-mode biasing network comprises a current-to-voltage converter for converting the reference current into a reference voltage, a low-pass filter for filtering the reference voltage into a filtered reference voltage, and a source follower for receiving the filtered reference voltage and outputting a biasing voltage. The oscillator core comprises a resonator coupled to a regenerative network. In an embodiment, the current-to-voltage converter comprises at least a diode-connected transistor.