High-speed high-precision comparator circuit design

A comparator circuit, high-precision technology, applied in CAD circuit design, instruments, calculations, etc., can solve the problems of increasing clock load and slowing down the comparator speed, so as to reduce clock load, improve driving ability, and equivalent input offset The effect of voltage reduction

Active Publication Date: 2018-04-20
SOUTHEAST UNIV
View PDF6 Cites 22 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In recent years, the second-order dynamic comparator widely used in ADCs uses two-phase non-overlapping clocks to realize the reset and comparison of the comparator. This method will increase the clock load and slow down the speed of the comparator.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • High-speed high-precision comparator circuit design
  • High-speed high-precision comparator circuit design
  • High-speed high-precision comparator circuit design

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0019] The present invention will be further described below in conjunction with the accompanying drawings.

[0020] Such as figure 1 Shown is a traditional dynamic comparator, which mainly completes the reset and comparison processes of the comparator by the clock signal CLK. In the reset phase, the CLK signal is low level, the tail current tube Mtail is disconnected, and the power supply voltage Vdd pulls the output OUTp and OUTn to high level Vdd through the comparator reset tubes M7 and M8; in the comparison phase, the CLK signal is high level At this time, the reset tube is cut off, and the difference between the input signal VIN and VIP is quickly amplified by the positive feedback latch stage composed of M3-M5, and one end of the output is pulled down to a low level, and the other end is kept at a high level.

[0021] Such as figure 2 Shown is a second-order dynamic comparator, which mainly includes a preamplifier and a positive feedback latch stage with a reset term...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses high-speed high-precision comparator circuit design. According to the design, a first-level regenerative amplifying circuit and a second-level positive feedback latching circuit are included. According to a comparator, by using the regenerative circuit in a first-level pre-amplifying process, the amplitude of a first-level output signal of the comparator reaches a degree capable of being recognized by a second positive feedback latching level in a shorter time, the speed of the comparator is increased, and therefore the comparator can be applied to a high-speed ADC (analog-digital converter). According to the second positive feedback latching level, two inverters are adopted to isolate the first level and the second level of the comparator, gain of the first-level regenerative amplifying circuit is improved, and equivalent input offset voltage of the comparator is lowered. Besides, compared with a second-order dynamic comparator adopted in the ADC, the load driving capability of the comparator is higher, and delay is more insensitive to changing of an input signal difference.

Description

technical field [0001] The invention relates to the field of analog CMOS integrated circuit design, in particular to a high-speed and high-precision comparator circuit design suitable for analog-to-digital converters. Background technique [0002] With the continuous development and progress of deep submicron process technology, high speed and low power consumption have become the two mainstream directions of current ADC development. As a key module of the ADC, the speed, offset and power consumption of the comparator play a decisive role in the performance of the entire ADC. The second-order dynamic comparator widely used in ADCs in recent years uses two-phase non-overlapping clocks to realize the reset and comparison of the comparator. This method will increase the clock load and slow down the speed of the comparator. Therefore, it is of great significance to reasonably design a comparator with faster speed and stronger driving capability. Contents of the invention [...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/36
Inventor 吴建辉王甫锋包天罡王鹏李红
Owner SOUTHEAST UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap