Field programmable gate array (FPGA) based multichannel high-speed image data acquisition and storage system

Abstract

The invention discloses an FPGA based multichannel high-speed image data acquisition and storage system. The system is characterized by comprising a signal conditioning module, an analog / digital (A / D) conversion module, a high-speed data transmission module, an FPGA control module, an array type storage module, a communication module and an adjustable configuration module. The signal conditioning module, the A / D conversion module, the high-speed data transmission module and the FPGA control module are connected successively. The FPGA control module is connected with the array type storage module, the communication module and the adjustable configuration module simultaneously and performs data interaction with an upper computer. The system is capable of achieving data capturing and rapid storage of high-speed image sensors and can be widely applied in data acquisition and storage with similar requirements of high speed, high accuracy, high data rate and multiple channels.

Description

technical field [0001] The invention relates to an FPGA-based multi-channel high-speed image data acquisition and storage system, and especially provides a high-speed, high-precision, multi-channel data acquisition and quick storage solution for the field of fast data acquisition and storage of high-speed image sensors. Background technique [0002] Acquisition and storage of high-speed image data is of great significance in the fields of industrial production, scientific research and national defense security. However, the currently commonly used scheme of using DSP or MCU to control ADC for data acquisition has the following disadvantages: [0003] 1. Limited by the instruction cycle of the microprocessor and the program-controlled sequence execution mechanism, ADC sampling cannot meet the requirements of high-speed, precise synchronization and concurrent image acquisition; [0004] 2. Limited by the speed of the external interface of the microprocessor, it does not suppo...

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Problems solved by technology

[0003] 1. Limited by the instruction cycle of the microprocessor and the program-controlled sequence execution mechanism, ADC sampling cannot meet the requirements of high-speed, precise synchronization and concurrent image acquisition;

[0004] 2. Limited by the speed of the external interface of the microprocessor, it does not support high-speed serial interface, and a large number of IO interfaces are required to achieve the same data bandwidth;

[0005] 3. As the image frame rate increases, the data bandwidth increases exponentially, which cannot solve the problem of fast storage of high-speed image data

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