BCH (Broadcast Channel) encoding and decoding method and device

An encoding method and encoding technology, which are applied in the field of BCH encoding and decoding methods and devices, can solve the problems of large delay in combinational logic, limiting the maximum frequency of encoders, and consuming too many XOR gates, etc.

Active Publication Date: 2012-07-04
LEADCORE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the process of realizing the above-mentioned BCH encoding and decoding, the inventors found that at least the following problems existed in the prior art: In terms of encoding, too many XOR gates were consumed, which resulted in too large combination

Method used

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  • BCH (Broadcast Channel) encoding and decoding method and device
  • BCH (Broadcast Channel) encoding and decoding method and device
  • BCH (Broadcast Channel) encoding and decoding method and device

Examples

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Embodiment 1

[0038] An embodiment of the present invention provides a BCH encoding method, such as figure 1 As shown, the BCH encoding method includes:

[0039] 101. A look-up table is set, and the coefficients of each level of the remainder polynomial are pre-stored in the look-up table, wherein the remainder polynomial is a bit-by-bit XOR operation between the high 8 bits of the current encoding status register and the current 8-bit encoding data, and the left The remainder of the polynomial pair generator polynomial obtained by shifting 104 bits;

[0040] 102. According to the current state of the encoding state register and the 8-bit data to be encoded, combined with the lookup table, obtain the state of the encoding state register at the next moment.

[0041] At the same time, the embodiment of the present invention also provides a BCH encoding device, including:

[0042] The setting module 201 is used to set the look-up table, and the coefficients of each level of the remainder pol...

Embodiment 2

[0046] An embodiment of the present invention provides a BCH decoding method, such as image 3 As shown, the BCH decoding method includes:

[0047] 301. Read all the check segment data located in the page redundancy area in the flash memory, and store it in the data buffer;

[0048] 302. Read multiple information segment data in the page information area in the flash memory;

[0049] 303. Record the error information of each BCH code according to the accompanying formula corresponding to each information segment data, and store the error information in a data buffer;

[0050] 304. The system-on-chip data reader completes error correction according to the error information.

[0051] At the same time, the embodiment of the present invention also provides a BCH decoding device, such as Figure 4 shown, including:

[0052] The first reading module 401 is used to read all the parity segment data located in the redundant area of ​​the page in the flash memory, and store it in th...

Embodiment 3

[0058] An embodiment of the present invention provides a BCH encoding method, such as Figure 5 As shown, the BCH encoding method includes:

[0059] 501. Set up a lookup table, the coefficients of each level of the remainder polynomial are pre-stored in the lookup table, wherein the remainder polynomial is a bit-by-bit XOR operation between the upper 8 bits of the current encoding status register and the current 8-bit encoding data, and the left The remainder of the polynomial pair generator polynomial obtained by shifting 104 bits;

[0060] The remainder polynomial is calculated as follows:

[0061] Let C(x) be any polynomial with the highest order of 103, namely:

[0062] C(x)=C 103 x 103 +C 102 x 102 +...+C 1 x+C 0 (1)

[0063] Then, C(x) can be expressed in either of the following two forms:

[0064] C ( x ) = x 96 C H ...

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Abstract

The invention discloses a BCH (Broadcast Channel) encoding and decoding method and a device. The BCH encoding method comprises the following steps of: setting a lookup table; pre-storing all levels of coefficient of a residue polynomial in the lookup table; and combining the lookup table to obtain a state of an encoding state register at the next moment according to the state of the encoding state register at the present moment and 8-bit data to be encoded. Meanwhile, the embodiment of the invention also provides a BCH decoding method, comprising the following steps of: reading data of all verification sections of a page redundancy area in a flash memory and storing the data into a data cache; reading the data of a plurality of information sections of a page information area in the flash memory; determining the position of each error according to the corresponding accompany type of the data in each information section and storing the positions of the errors into the data cache; and finishing error correction by a data reading part of an on-chip system according to the error information in the data cache. The BCH encoding and decoding method and the device are suitable for the BCH encoding and decoding of the flash memory application facing to the on-chip system.

Description

technical field [0001] The invention relates to the field of on-chip systems, in particular to a BCH encoding and decoding method and device. Background technique [0002] In recent years, due to the popularity of various handheld devices, the widespread use of Flash memory (flash memory) has been driven. However, due to its own physical characteristics, the stability of Flash memory is poor. After repeated erasing and writing, the probability of errors will gradually increase. ; On the other hand, with the progress of new technology and technology, the memory unit of Flash has gradually shifted from SLC (Single-level Cell, single-level cell) structure to MLC (Multi-level Cell, multi-layer cell) structure, thereby bringing Compared with SLC, the error probability and number of errors of each Page in Flash are greatly increased. In order to ensure the correctness of data storage, appropriate error-correcting code technology must be adopted. BCH code is a widely used and eff...

Claims

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Application Information

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IPC IPC(8): H03M13/15H04L1/00
Inventor 施旺根
Owner LEADCORE TECH
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