FPGA implementation device and method based on FBLMS algorithm of block floating points

A block floating-point and algorithmic technology, applied in computing, instrumentation, electrical digital data processing, etc., can solve problems such as consuming hardware resources and difficult implementation of complex algorithms

Active Publication Date: 2020-08-07
INST OF AUTOMATION CHINESE ACAD OF SCI +1
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Problems solved by technology

Based on the above advantages, FPGA has been widely used in the hardware implementation of various signal processing algorithms. However, FPGA has shortcomings

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  • FPGA implementation device and method based on FBLMS algorithm of block floating points
  • FPGA implementation device and method based on FBLMS algorithm of block floating points
  • FPGA implementation device and method based on FBLMS algorithm of block floating points

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Embodiment Construction

[0080] The application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain related inventions, not to limit the invention. It should also be noted that, for the convenience of description, only the parts related to the related invention are shown in the drawings.

[0081] It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0082] A kind of FPGA realization device of FBLMS algorithm based on block floating point of the present invention, this device comprises input buffer conversion module, filter module, error calculation and output buffer module, weight value adjustment calculation module, weight valu...

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Abstract

The invention belongs to the technical field of real-time adaptive signal processing, particularly relates to an FPGA implementation device and method of an FBLMS algorithm based on a block floating point, and aims to solve the problem that conflicts exist among performance, speed and resources when an existing FPGA device implements the FBLMS algorithm. The method comprises the following steps that an input cache transformation module performs block cache recombination on a reference signal, converts the reference signal into block floating points and then performs FFT transformation; a filtering module carries out filtering in a frequency domain and carries out dynamic bit cutting; an error calculation and output caching module performs block caching on the target signal, subtracts the filtered output after the target signal is converted into a block floating point, and converts the result into a fixed-point system to obtain a final cancellation result; and a weight adjustment calculation module and a weight update storage module obtain the adjustment amount of the weight and update the weight block by block. Aiming at a recursive structure of the FBLMS algorithm, a block floating point data format and a dynamic bit cutting method are adopted, so the data is ensured to have a large dynamic range and high precision, conflicts among performance, speed and resources are solved,and the reusability and expansibility are also improved through modular design.

Description

technical field [0001] The invention belongs to the technical field of real-time self-adaptive signal processing, and in particular relates to an FPGA implementation device and method of a FBLMS algorithm based on block floating points. Background technique [0002] Theoretical research and hardware implementation of adaptive filtering algorithm has been one of the research hotspots in the field of signal processing. When the statistical characteristics of the input signal and noise are unknown or change, the adaptive filter can automatically adjust its own parameters under the premise of meeting certain criteria, and always achieve optimal filtering. Adaptive filters have been widely used in many fields such as signal detection, digital communication, radar, engineering geophysical prospecting, satellite navigation and industrial control. From the point of view of system design, the amount of computation, structure, and robustness are the three most important criteria for ...

Claims

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Application Information

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IPC IPC(8): G06F7/57
CPCG06F7/57G06F7/4876G06F30/34G06F17/142
Inventor 赵良田蒿杰宋亚芳舒琳马赛范秋香冯卉
Owner INST OF AUTOMATION CHINESE ACAD OF SCI
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