Execution method for logarithmic loading instruction

Abstract

The invention discloses an execution method for a logarithmic loading instruction. The method comprises the steps of extracting an LDP instruction, splitting the LDP instruction into two micro-operations with destination registers, performing decoding, register renaming and assignment by taking the micro-operations as units, assigning items for the two micro-operations in a reorder buffer during assignment, and combining the two micro-operations in a transmission queue; if two data loading pipelines are available, transmitting an LDP after combination to an memory access unit, and performing execution in the first data loading pipeline; after the execution, writing back a low half part of obtained data to the first destination register through a result bus of the first data loading pipeline, and writing back a high half part to the second destination register through a result bus of the second data loading pipeline; and finally submitting the two micro-operations to release resources.On the premise that data access times are not increased, the number of destination register channels can be reduced, the design complexity can be lowered, and the area expenditure can be reduced.

Description

technical field [0001] The invention relates to the field of microprocessor design, in particular to an execution method of a logarithmic load instruction in the design of an out-of-order superscalar microprocessor. Background technique [0002] For an instruction set architecture, most instructions have no more than one destination register. However, some instruction set architectures provide a pair of load instructions. We use the mnemonic LDP Rd1, Rd2, Xn, #offset to represent the instruction, where Rd1 and Rd2 are the destination registers, Xn is the memory base address, and #offset is the address offset. Shift, hereinafter also use LDP as the abbreviation of logarithmic load instruction. The logarithmic load instruction has two destination registers, namely Rd1 and Rd2, which means to read data whose width is twice the width of a destination register from address [Xn+offset], and store the lower half of the data into Rd1 , the high half is stored in Rd2. Because LDP ...

AI Technical Summary

Problems solved by technology

In order to support a pair of load instructions, the maximum number of rename registers released per beat will be doubled, thereby increasing the design complexity of the logic

[0005] In the known out-of-order superscalar mi

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