Method for renaming state register and processor using the method

A technique of register renaming and status register, applied in machine execution devices, concurrent instruction execution, etc.

Active Publication Date: 2008-04-30
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] A large number of modern processors use both pipeline and superscalar technologies to obtain higher performance. However, in practice, there may be some data dependencies between instructions, such as a The source operand that needs to be read by the ins

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  • Method for renaming state register and processor using the method
  • Method for renaming state register and processor using the method
  • Method for renaming state register and processor using the method

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Embodiment Construction

[0029] Apparatuses and methods for renaming flag registers are described herein. In order to solve the pipeline stall problem caused by the implicit read and write of the flag register, in the following description, some related specific details are given to provide a better understanding of the present invention.

[0030] figure 1 A partial structure diagram of a processor implementing the renaming mechanism is given. As shown in the figure, the structure mainly includes the following modules:

[0031] The instruction fetching module 100 fetches the next instruction to be executed according to the given pc value, and sends it to the pipeline for execution;

[0032] The decoding module 101 decodes the macroinstructions sent by the instruction fetching module to generate one or more microcode formats represented internally by the processor. The macroinstructions are in the instruction set format compatible with the corresponding processor, such as an x86 architecture processor...

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Abstract

The invention provides a method for renaming a status register in a superscalar processor with a pipeline structure, wherein the status register is a register composed of a plurality of flag bits selected from all flag bits of a flag register. The method comprises determining whether a microcode will read the status register when the microcode coded by a command reaches a register renaming module of the processor; if determining that the microcode will read the status register, allocating a nearest mapping physical register for the status register; otherwise, not allocating the physical register for the status register; determining whether the microcode will be written to the status register; if determining that the microcode will be written into the status register, allocating a new physical register with empty status to the status register; and otherwise, not allocating the physical register for the status register.

Description

technical field [0001] The present invention relates to microprocessor architecture, in particular to a method for renaming state registers in a processor with a superscalar pipeline structure and a processor using the method, which can rename the registers In order to improve the execution efficiency of the pipeline structure processor, the method can eliminate the false data correlation in the execution of the instruction, and can easily realize the renaming mechanism of the flag register to reduce the pipeline stall caused by reading and writing the flag bit. Background technique [0002] In the design of modern microprocessors, the throughput rate of instructions, that is, the number of instructions that can be executed per second, is a very important indicator. There are many ways to measure the number of instructions per unit time. The most direct technique is to increase the number of processors running However, an increase in frequency will lead to a rapid increase i...

Claims

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Application Information

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IPC IPC(8): G06F9/38
Inventor 叶笑春段振中范东睿张军超
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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