Register renaming system and method for managing and renaming registers

Abstract

The invention relates to a register renaming system and method for managing and renaming registers. The invention specifically provides the register renaming system for managing and renaming the registers by adopting multiple renamed register queues, and the system comprises a physical register group, a register alias table (RAT), an architecture register mapping table (ARMT), a select finger of the renamed register queues, a decoder, a logic register renaming device, an RAT modifying device and an updating device of the renamed register queues. In addition, the invention further provides the method for managing and renaming the registers by adopting the multiple renamed register queues. According to the technical scheme provided by the invention, renaming operation can be simultaneously performed on the multiple registers within a same period, the implementation method is simple, the time cost is small, and the register renaming system and method are suitable for superscalar microprocessors with higher transmission width.

Description

technical field [0001] The present invention relates to the technical field of microprocessor architecture, in particular to a register renaming system and method using multiple renaming register queues. Background technique [0002] Most modern microprocessor architectures use super scalar (Super Scale) technology, that is, in one cycle, multiple pipelines execute multiple instructions in parallel. Register Renaming technology is one of the key technologies of superscalar microprocessors. It solves the problem of read-after-write (WAR) and write in program operation by mapping the same logical register to multiple physical registers. Write (WAW) data correlation, greatly improving the parallel execution of instructions. [0003] One of the implementations of the register renaming operation is to use an Architecture Register Mapping Table (ARMT for short) for a set of physical registers to store the correspondence between physical registers and logical registers. The logic...

AI Technical Summary

Problems solved by technology

[0005] With the increase of the launch width of superscalar microprocessors, the renaming engine is required to perform multiple renaming operations in one cycle, which requires that multiple free renaming registers can be searched in one cycle, and the larger The launch width also requires more physical registers to be used for register renaming operations, increasing the workload of the renaming engine to search for free registers, making the renaming engine a bottleneck affecting the frequency increase of the microprocessor

[0006] For the search of free registers, the traditional search method is to search for the next free register after finding a free register. The search of different free registers is in a serial relationship in timing, similar to the carry chain of an adder, so when the candidate When there are a large number of physical registers and multiple search results are required, a large delay will be generated, which will affect the improvement of the operating frequency of the microprocessor.

Images