Multi-instruction out-of-order transmitting method based on instruction withering and processor

Abstract

The invention discloses a multi-instruction out-of-order transmitting method based on instruction withering and a processor, and belongs to the field of processor design. According to the invention, aredundant arbitration structure in a traditional transmitting architecture is abandoned, an instruction withering circuit is added, and an instruction age array is adopted to represent the storage time of instructions in a CPU. In addition, an awakening state bit is added, the instructions exceeding the withering threshold value are stored in a settling pond so that a CPU can directly transmit the instructions, circuit structures such as an instruction request circuit, an instruction distribution circuit and an awakening circuit are improved, and the time sequence of a key path in the processor for multi-instruction transmission is effectively improved; and when an instruction is awakened, delayed awakening is performed on an instruction with a short execution period, the instruction witha long execution period is awakened in advance so as to ensure that the instruction can be executed back to back, the requirements of high power consumption ratio, low delay and high IPC in a modernsuperscalar out-of-order processor are met, and the problems that in the prior art, the number of items of a launch queue table of a processor cannot be increased day by day, and delay is also increased day by day are solved.

Description

technical field [0001] The invention relates to a multi-instruction out-of-sequence emission method based on instruction withering and a processor, belonging to the field of processor design. Background technique [0002] CPUs have been particularly slow to improve in single-core performance in the over a decade since the Dennard scaling ended. In this context, it is absolutely necessary to re-study the core microarchitecture to achieve high single-core performance. [0003] Among the many structures of the CPU, the instruction emission architecture is one of the important architectures to realize the high performance of the CPU. The instruction issue architecture schedules instructions for execution by selecting and issuing instructions from the instructions to issue in the instruction issue queue each cycle. In order to achieve high performance, the instruction launch architecture must achieve high IPC (Instructions per clock, the number of instructions executed per cycl...

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Problems solved by technology

[0008] In order to solve the problem that the delay of the arbitration circuit will increase correspondingly with the increase of the number of items in the launch queue in the current method of selecting instructions that can be transmitted through the arbitration circuit, the present invention provides a multi-command out-of-sequence transmission method based on command withering and processor

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