Neural network accelerator compiling method and device

Abstract

The invention provides a neural network accelerator compiling method and device, and the method comprises the steps: generating a dependency relationship between preset instruction types and a plurality of neural network compiler instruction queues based on neural network structure information and preset instruction types, wherein the neural network compiler instruction queue is a queue composed of neural network compiler instructions of the same preset instruction type; according to the dependency relationship, determining a parallel operation strategy between the neural network compiler instruction queues; and generating an acceleration instruction of the neural network accelerator according to the parallel operation strategy. According to the method and device, flexible dynamic adjustment technologies such as the circular buffer and the superscale are fused in the accelerator special for the neural network, so that the problems of neural network parameter loading and module utilization rate can be effectively solved, and the neural network can be deployed at the edge end more quickly.

Description

technical field [0001] The invention relates to the technical field of artificial intelligence, in particular to a method and device for compiling a neural network accelerator. Background technique [0002] At present, artificial intelligence (AI) technology is advancing by leaps and bounds. Deep neural networks suitable for complex tasks such as identification, detection, and tracking are used in various industries. In order to deploy AI algorithms at the edge and achieve end-cloud collaboration, embedded The rapid development of neural network processor technology. [0003] Neural network reasoning is expensive in terms of computation and space. In order to support edge hardware with low power consumption and low computing power, compression techniques such as quantization learning and sparse pruning have been proposed in large numbers, and operators such as convolution are also implemented at the edge. parallel operation. Among them, quantitative learning replaces the f...

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Problems solved by technology

[0004] However, quantization learning, sparse pruning and other technologies reduce the size of the neural network network during the training and inference stage, and have not been optimized in conjunction with the neural network-specific accelerators at the edge.

The calculation of the neural network algorithm at the edge is still inefficient and has poor versatility. The data transmission between different layers still needs to consume a lot of redundant resources, and the utilization rate of each module still has a lot of room for improvement. At the same time, the accelerator runs Sinking the instruction set from the cloud to the edge requires complex adjustments, and it is far from being able to meet real-time requirements only through convolutional hardware acceleration

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