Acceleration processing unit based on convolutional neural network and array structure thereof

A convolutional neural network and processing unit technology, applied in the field of accelerated processing units and array structures, can solve the problems of increased processing speed, high power consumption, large chip area of ​​accelerated processing units, etc., and achieve the goal of small on-chip area and reduced use Effect

Inactive Publication Date: 2016-12-07
HARBIN INST OF TECH SHENZHEN GRADUATE SCHOOL +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The existing accelerated processing unit is designed with an adder and a multiplier for each input multimedia data. When the accelerated processing unit needs to process multiple local data, it means that each accelerated processing unit includes multiple additions. multiplier and multiple multipliers, this design leads to a large area of ​​the accelerated processing unit chip, high power consumption, and the processing speed needs to be improved

Method used

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  • Acceleration processing unit based on convolutional neural network and array structure thereof
  • Acceleration processing unit based on convolutional neural network and array structure thereof
  • Acceleration processing unit based on convolutional neural network and array structure thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0031] Please refer to figure 1 , the present embodiment provides an accelerated processing unit based on a convolutional neural network. The accelerated processing unit 61 includes a first register 21, a second register 22, a third register 23, a fourth register 24, a fifth register 25, and a multiplier 41 , adder 51 and first multiplexer 31 and second multiplexer 32.

[0032] The first register 21 is connected to an input end of the multiplier 41 , and the first register 21 is used for inputting multimedia data and sending the multimedia data to the multiplier 41 . The second register 22 is connected to the other input terminal of the multiplier 41 , and the second register 22 is used to input the filter weight and send the filter weight to the multiplier 41 . The output terminal of the multiplier 41 is connected to the third register 23 for multiplying the multimedia data and the filter weight, and sending the multiplied result to the third register 23 .

[0033] The firs...

Embodiment 2

[0047] Please refer to Figure 3 to Figure 5 , showing an array structure based on a convolutional neural network, including multiple accelerated processing units, the multiple accelerated processing units are in the form of a matrix with M rows and N columns, where M and N are integers greater than or equal to 1 , the accelerated processing units of each column are connected back and forth.

[0048] In this embodiment, multiple accelerated processing units are in the form of a matrix of 3 rows and 3 columns. In each column, the output end of the adder of the previous accelerated processing unit is connected to the first multiplexer of the next accelerated processing unit. Three ends.

[0049] In the accelerated processing units in the same row, the input filter weights are the same; in the accelerated processing units located in the same diagonal line, the input local data are the same.

[0050] In the accelerated processing units of different rows, the input filter weights...

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Abstract

The invention discloses an acceleration processing unit based on a convolutional neural network, and is used for performing convolution operation on local data. The local data include multiple multimedia data. The acceleration processing unit comprises a first register, a second register, a third register, a fourth register, a fifth register, a multiplier, an adder, a first multipath selector and a second multipath selector. The single acceleration processing unit controls the first multipath selector and the second multipath selector so that the multiplier and the adder are enabled to be repeatedly usable, one acceleration processing unit is enabled to only need one multiplier and one adder to complete convolution operation and use of the multiplier and the adder can be reduced. Processing speed can be enhanced and energy consumption can be reduced by reducing use of the multiplier and the adder in implementing the same convolution operation, and the on-chip area of the single acceleration processing unit is smaller.

Description

technical field [0001] The invention relates to a convolutional neural network, in particular to an accelerated processing unit and an array structure in a convolutional layer of the convolutional neural network. Background technique [0002] Compared with shallow learning, deep learning (dee acceleration processing unit Plea2ning) means that the machine learns the rules from historical data through algorithms, and makes intelligent identification and prediction of things. [0003] Convolutional Neural Network (Convolutional Neu2al Netwo2k, CNN) is a kind of dee accelerated processing unit Plea2ning netwo2k, which was invented in the early 1980s. It is composed of artificial neurons arranged in multiple layers. The convolutional neural network reflects the human brain processing vision. Methods. As Moore's Law drives computer technology to become more and more powerful, convolutional neural networks can better imitate the actual operation of biological neural networks, avoi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/02G06F9/28
CPCG06F9/28G06N3/02
Inventor 宋博扬赵秋奇马芝刘记朋韩宇菲王明江
Owner HARBIN INST OF TECH SHENZHEN GRADUATE SCHOOL
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