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Microprocessor, and method of executing fused composite arithmetical operation therein

A microprocessor and arithmetic operation technology, which is applied in machine execution devices, concurrent instruction execution, electrical digital data processing, etc., can solve problems such as performance disadvantages

Active Publication Date: 2017-02-15
VIA ALLIANCE SEMICON CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] However, in cases where adders and multipliers of multiple split FMA functions share the same dispatch port, the above configuration suffers a performance disadvantage when FMA instructions saturate the pipeline

Method used

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  • Microprocessor, and method of executing fused composite arithmetical operation therein

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Embodiment Construction

[0038] The following description is presented to enable one of ordinary skill in the art to make and use the invention as presented within the context of the particular application and its requirements. However, various modifications to the preferred embodiment will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments as well. Thus, the present invention is not intended to be limited to the particular embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0039] Figure 1-8 Various aspects of various embodiments of the invention are illustrated. figure 1 was applied from '817 figure 1 modified, and use consistent reference numerals. Since the '817 application uses reference numerals up to 500, the present application Figure 2-8 Reference numbers starting with the 600 range are used from the end of the '817 a...

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Abstract

The invention relates to a microprocessor and a method of executing fused composite arithmetical operation therein. The microprocessor is configured for a non-chain mode and a chain mode of splitted execution of the composite arithmetical operation; in the two modes of hte splitted execution, a first command executing unit only executes a first part in the fused composite arithmetical operation and generates an inter-result thereof; and a second command executing unit receives the inter-result and executing a second part in the fused composite arithmetical operation so as to obtain a final result. In the non-chain mode, independent splitted execution micro-commands are distributed to the first and the second command executing units to achieve the execution. In the chain mode, single splitted execution micro-command is distributed to the first command executing unit, and a chain-type control signal or signal group is sent to the second command executing unit so that the second command executing unit, without commands, executes the second part of hte fused composite arithmetical operation, thus achieving execution.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Provisional Patent Application 62 / 236,529, filed October 2, 2015, which is hereby incorporated by reference. [0003] This application is related to U.S. Patent Application 14 / 748,817, entitled "Non-atomic Split-Path FusedMultiply-Accumulate," filed June 24, 2015 (the "'817 application"), which claims the July 2, 2014 U.S. Provisional Patent Application 62 / 020,246, filed on June 10, 2015, entitled "Non-Atomic Split-Path Fused Multiply-Accumulate with Rounding cache" and entitled "Non-Atomic Temporally-Split Fused Multiply-Accumulate with Rounding cache" and Operation Using a Calculation Control Indicator Cache and Providing a Split-Path Heuristic for Performing a Fused FMA Operation and Generating a StandardFormat Intermediate Result", which are hereby incorporated by reference in their entirety. [0004] This application is also related to and incorporates by reference the following...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/544G06F7/575G06F9/22G06F9/28G06F9/302G06F9/38
CPCG06F7/5443G06F7/575G06F9/223G06F9/28G06F9/3001G06F9/3867G06F9/3887G06F9/3893G06F9/30014G06F9/3836
Inventor 汤玛士·艾欧玛尼基尔·A·帕蒂尔
Owner VIA ALLIANCE SEMICON CO LTD
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