146results about How to "Small circuit size" patented technology

A current direction detection circuit includes a monitoring transistor having a control terminal and an output terminal respectively connected with a control terminal and an output terminal of a ground side output transistor; an impedance element having one terminal connected with an input terminal of the monitoring transistor and the other terminal grounded; first and second constant-current sources; a diode-connected reference transistor interposed between the first constant-current source and ground potential; and a sensing transistor interposed between the second constant-current source and the impedance element and having a control terminal connected with the control terminal of the reference transistor. The current direction detection circuit is small yet capable of minimizing power loss of a switching regulator.

A bypass control section (6) maintains a bypass switch (5) in the ON state during the period when a battery voltage (Vi) is higher than the output voltage (Vo) to an external load (L). Upon falling of the output voltage (Vo) at a desired voltage (ET), a converter control section (4) starts switching control at once, and a step-up chopper (3) promptly starts boost operation. The bypass control section (6) maintains the bypass switch (5) in the ON state from the start of the boost operation of the step-up chopper (3) until the match between the battery voltage (Vi) and the output voltage (Vo).

An LCD device according to the present invention has: an LCD panel; an operation and correction circuit configured to perform a correction operation with respect to an input gray-scale data of a target frame image by using an arithmetic expression to generate an output gray-scale data; a data line driver configured to drive the LCD panel in accordance with the output gray-scale data; and a correction data calculation circuit configured to generate a correction data that specifies a relationship between the input gray-scale data and the output gray-scale data of the target frame image, depending on the input gray-scale data of the target frame image or an input gray-scale data of a precedent frame image followed by the target frame image. The operation and correction circuit determines coefficients of the arithmetic expression from the correction data.

A bypass control section (6) maintains a bypass switch (5) in the ON state during the period when a battery voltage (Vi) is higher than the output voltage (Vo) to an external load (L). Upon falling of the output voltage (Vo) at a desired voltage (ET), a converter control section (4) starts switching control at once, and a step-up chopper (3) promptly starts boost operation. The bypass control section (6) maintains the bypass switch (5) in the ON state from the start of the boost operation of the step-up chopper (3) until the match between the battery voltage (Vi) and the output voltage (Vo).

Disclosed is an OFDM signal receiving apparatus for diversity reception, with a plurality of antennas, of an OFDM signal containing Y sub-carriers, where 2X−1<Y<2X and X>1. The OFDM signal receiving apparatus includes a plurality of receiving systems, and a diversity processing unit connected to the receiving systems and fed with sequences of data on sub-carriers demodulated by the respective receiving systems. At least one of the receiving systems includes an FFT circuit for Fast Fourier transforming, in parallel, only a sequence of data on 2Z sub-carriers contained in the OFDM signal received with a corresponding antenna, where X>Z. The diversity processing unit performs a diversity process on sequences of data on sub-carriers, out of all the Y sub-carries, redundantly demodulated.

The amounts of liquid discharged from a liquid discharge head to predetermined areas can be made uniform while suppressing an increase in circuit size. In order to achieve this object, there is provided a liquid discharge apparatus which discharges a liquid from a liquid discharge head having a plurality of nozzles for discharging the liquid, wherein the liquid discharge head includes a subset of nozzles capable of individually controlling liquid discharge amounts, among the plurality of nozzles. The subset of nozzles is smaller in number than the total number of the plurality of nozzles.

With the aim of quickly returning the voltage of an output line to an ultrasonic transducer from a positive voltage or a negative voltage to the ground voltage and reducing the circuit size, immediately after turning on and turning off of a positive FET in accordance with a positive pulse signal, a negative FET goes on for only a pull-back period allowing for the output line to return to the ground voltage. Also, immediately after turning on and turning off of the negative FET in accordance with a negative pulse signal, the positive FET goes on for only a pull-back period allowing for the output line to return to the ground voltage.

The invention relates to a high-efficiency LED constant current driving circuit. The circuit comprises an input rectification filter circuit, a switch power supply management chip, an isolation switch transformer, a primary clamping circuit of the transformer, an output rectification filter circuit, an output current sampling circuit, a reference voltage generation circuit, a comparison circuit and a photoelectrical coupling circuit, wherein the input end of the input rectification filter circuit is connected with commercial AC electricity, while the output end is connected with a primary winding of the isolation switch transformer through the switch power supply management chip; the primary clamping circuit of the transformer is connected in parallel with the primary winding of the isolation switch transformer; the input end of the output rectification filter circuit is connected with the primary winding of the isolation switch transformer, while the output end is connected with LED load; an output current sampling circuit is connected in series with the LED load; the input end of the reference voltage generation circuit is connected with the LED load; and the input end of the comparison circuit is connected with the output current sampling circuit and the reference voltage generation circuit, while the output end is connected with the switch power supply management chip through the photoelectrical coupling circuit. The circuit improves the circuit integration degree, the reliability, the constant current precision and the circuit conversion efficiency.

A device, in which circuit size is small and operation is stable, comprises a plurality of serially connected unit registers (shift registers) in which transfer is controlled by any of three or more clock signals each having a different phase, and a setting signal which determines shift direction; and a selection circuit (switch array) which can select at least one clock signal from the three or more clock signals in accordance with the setting signal; wherein the unit registers are put in a reset state by one clock signal selected by the selection circuit, corresponding to each of the unit registers

A light source driving circuit for a backlight module is disclosed, wherein each driving unit includes a reference resistor, a transistor, a bias resistor and a shunt regulator. The transistor is coupled between an LED string and the reference resistor, and the bias resistor is coupled between an operation voltage and the control terminal of the transistor. The shunt regulator is coupled between the control terminal of the transistor and a common terminal, and the reference pin of the shunt regulator is coupled to the common node between the reference resistor and the transistor.

The digital camera (100) has an image processor that corrects an input image for a spatial frequency band. The edge enhancement block (106) computes an edge component for band correction. A signal interpolated at color interpolation block (107) to make compensation for a color component missing from each pixel of a single-chip image is then converted at YC transform block (108) into a luminance signal and a color difference signal after tone correction, the luminance and color signals sent out to YC synthesis block (110) and color saturation correction block (109), respectively. Then, the color saturation correction block (109) controls the color saturation of the color difference signal to send it out to YC synthesis block (110). At the same time, the edge component computed at edge enhancement block (106) is sent out to YC synthesis block (110), too.

A nonperiodic waveform is forced to a periodic character to facilitate looping of the waveform without introducing audible, and thus objectionable, sound artifacts. Nonperiodic waveforms are typically nonperiodic due to the presence of nonharmonic high frequency spectral components. In time, the high frequency components decay faster than low frequency components and looping of the waveform is facilitated. A loop forcing process and loop forcing filter facilitate looping of a nonperiodic waveform by accelerating the removal of the nonperiodic high frequency components. A loop forcing filter accelerates the removal of nonperiodic high frequency components using a comb filter having a frequency selectivity that varies in time.

A predistorter for the linearization of a power amplifier is provided. The predistorter can incorporate a field effect transistor (FET), which permits a design having low power consumption and broad band characteristics. The predistorter can be appropriate for integration with the power amplifier, unlike the conventional predistorters, because the subject predistorter does not significantly increase the size and complexity of the wireless system. In an embodiment, the subject predistorter can be coupled with a gate bias circuit of a power amplifier. When the predistorter is coupled with the gate bias of a power amplifier, the predistorter can function as linearizer as well as an adaptive gate bias circuit.

A power factor correction converter and a power factor correction conversion device, includes two groups of bidirectional switches, an autotransformer, a boost inductor, a bus filter capacitor, two front bridge arms; and a rear bridge arm; the front end of each group of bidirectional switches are connected to a coil of the autotransformer in one-to-one correspondence, and a rear end of each group of bidirectional switches is connected to one end of an AC input power grid; a central tap of the autotransformer is connected to an output end of the boost inductor, and an input end of the boost inductor is connected to the other end of the AC input power grid; a front end of each group of bidirectional switches is connected to a front bridge arm, and a rear end is connected to the rear bridge arm.

A semiconductor device, includes: a semiconductor substrate; a multilayered interconnect structure formed on the semiconductor substrate; a terminal for flip-chip packaging arranged on the surface of the multilayered interconnect structure; and a spiral inductor formed to enclose the terminal for flip-chip packaging, in a plan view, which is not electrically connected with the spiral inductor. The spiral inductor may be provided for peaking by which the gain reduction caused in a high frequency is compensated.

Each of N optical detector parts 801 to 80N has a photodiode PD, a capacitor Cd and a switch SW0. An amplifier A1, an integrator circuit capacitor Cf1, and a switch SW11 , are connected in parallel between the input terminal and the output terminal of an integrator circuit 10. The capacitance of the integrator circuit capacitance C11 is equal to the capacitance of the capacitor Cd in each of the N optical detector parts 801 to 80N. A switch SW01, is equipped between the input terminal of the integrator circuit 10 and the switch SW0 for each of the N optical detector parts 801 to 80N. A switch SW02 is equipped between the output terminal of the integrator circuit 10 and the switch SW0 in each of the N optical detector parts 801, to 80N.

A modulated signal is generated by performing pulse modulation of a drive waveform signal that is a reference for a drive signal to be applied to a capacitive load, and the drive signal is generated by performing power amplification of the acquired modulated signal and then smoothing the power-amplified modulated signal. Then, negative feedback of the drive signal applied to the capacitive load is applied to the drive waveform signal that is the reference for the drive signal. At this time, a predetermined analog compensation process for smoothing gain characteristics in a frequency band included in the drive signal is performed for the drive signal, then the acquired signal is converted into a digital signal, and negative feedback of the digital signal is applied to the drive waveform signal.

A receiver includes an oscillator for generating a local oscillator signal, a frequency converter for heterodyning a received signal of one frequency band or a plurality of frequency bands into an intermediate frequency (IF) signals with using the local oscillator signal, a filter connected to an output of the frequency converter and having a cut-off frequency changeable, an analog-digital (AD) converter connected to an output of the filter to convert an analog signal of one frequency band or a plurality of frequency bands into a digital signal, a pre-stage detector connected to an output of the AD converter or connected between the filter and the AD converter to detect a signal level, and a controller for controlling the cut-off frequency of the filter based on the signal level detected by the pre-stage detector.

In each photosensitive cell, a photodiode 101, a transfer gate 102, a floating diffusion layer section 103, an amplifier transistor 104, and a reset transistor 105 are formed in one active region surrounded by a device isolation region. The floating diffusion layer section 103 included in one photosensitive cell is connected not to the amplifier transistor 104 included in that cell but to the gate of the amplifier transistor 104 included in another photosensitive cell adjacent to the one photosensitive cell in the column direction. A polysilicon wire 111 connects the transfer gates 102 arranged in the same row, and a polysilicon wire 112 connects the reset transistors 105 arranged in the same row. For connection in the row direction, only polysilicon wires are used.

The digital camera (100) has an image processor that corrects an input image for a spatial frequency band. The edge enhancement block (106) computes an edge component for band correction. A signal interpolated at color interpolation block (107) to make compensation for a color component missing from each pixel of a single-chip image is then converted at YC transform block (108) into a luminance signal and a color difference signal after tone correction, the luminance and color signals sent out to YC synthesis block (110) and color saturation correction block (109), respectively. Then, the color saturation correction block (109) controls the color saturation of the color difference signal to send it out to YC synthesis block (110). At the same time, the edge component computed at edge enhancement block (106) is sent out to YC synthesis block (110), too.

The invention discloses a double-frequency Wilkinson power divider. Impedance conversion is realized by using two sections of transmission lines, and the characteristic impedances of the two sections of transmission lines are respectively Z1 and Z2; an isolating resistor R is arranged between two output ports, the two output ports are respectively connected with one segment of open-circuit microstrip line in parallel, and the characteristic impedance of the open-circuit microstrip line is Z3. The isolation degree is increased by respectively connecting the two output ports with one segment of open-circuit microstrip line, and the required impedance is accurately realized by using the open-circuit microstrip lines. The invention has the advantages of small size and double-frequency operation; the required impedance is accurately realized by using the open-circuit microstrip lines, the analytical design formula of the double-frequency power divider is deducted by using odd-even mode analysis and double-frequency analysis, and the design is accurate; the power divider working in any two or more than two frequency ranges not only effectively reduces circuit size, but also reduces insertion loss and improves noise characteristics.

A semiconductor device (1) includes a non-volatile memory cell array (2), a write / read circuit (30) writing data into and reading data from the non-volatile memory cell array (2), a data input / output circuit (80), and a volatile memory cell array (40) including a first latch circuit (41) that is connected to the write / read circuit (30) and latches first data, and a second latch circuit (42) that is connected to the data input / output circuit (80) and latches second data. The device (1) may further include an inverter circuit (310) that inverts the first data in accordance with the number of bits to be actually written among the first data, and a control circuit (3) that causes the second data to be latched in the second latch circuit (42) while the first data is being written into the non-volatile memory cell array (2). This semiconductor device (1) has a shorter writing time and a smaller circuit area.

A semiconductor device includes: memory blocks each having groups of memory cells that are connected to word lines; select gates for selecting the groups of memory cells; and an apply circuit that applies, at the time of reading data, a back bias to the select gates of unselected memory blocks.

The invention discloses an ultrasound emitting system for high frequency ultrasonic diagnostic equipment, and belongs to the technical field of medical ultrasonic diagnosis technology. The ultrasound emitting system comprises a high frequency array ultrasonic transducer, a high voltage matrix switching circuit, an emitting driving circuit and a field programmable gate array (FPGA) control circuit, wherein the high voltage matrix switching circuit connects array elements of the high frequency array ultrasonic transducer with various emitting channels of the emitting driving circuit, and performs circular switching according to the scanning sequence of ultrasonic beams during ultrasonic imaging; the emitting driving circuit generates high voltage pulses to act on the high frequency array ultrasonic transducer to generate ultrasound; and the FPGA control circuit controls the switching between the high frequency array ultrasonic transducer and the various emitting channels of the emitting driving circuit to generate trigger pulses of the emitting driving circuit. The circuit volume of the whole ultrasound emitting system is reduced, the number of used components is greatly decreased and the hardware cost is effectively controlled.

A semiconductor device includes: memory blocks each having groups of memory cells that are connected to word lines; select gates for selecting the groups of memory cells; and an apply circuit that applies, at the time of reading data, a back bias to the select gates of unselected memory blocks.