CMOS full adder and multi-bit full adder

Abstract

The invention discloses a CMOS full adder. The CMOS full adder comprises more than one PMOS field effect transistor, more than one NMOS field effect transistor and a connecting circuit. The connectingcircuit is used for connecting the more than one PMOS field effect transistor and the more than one NMOS field effect transistor. The connecting circuit is configured to reduce a threshold voltage ofat least one of the more than one PMOS field effect transistor and the more than one NMOS field effect transistor. The invention further discloses a multi-bit full adder. The multi-bit full adder comprises a plurality of CMOS full adders. The CMOS full adder and the multi-bit full adder can effectively reduce the ascending, descending and propagation delay conditions of the device, thereby improving the circuit speed.

Description

technical field [0001] The present application relates to the field of adders, in particular to a CMOS full adder based on substrate bias and a multi-bit full adder composed of multiple CMOS full adders. Background technique [0002] With the development of Internet of Things technology, low power consumption circuit design has become the focus of research. One of the effective ways to reduce power consumption is to reduce the operating voltage of the circuit to near the near-threshold, thus forming a near-threshold circuit. But at a near-threshold voltage, the speed of many computing units in the circuit will be greatly reduced, or even fail to work properly. [0003] In the development of large-scale integrated circuits, data computing has always played an important role. The addition operation (including summation, subtraction, multiplication, division, exponent operation, etc.) as a common data operation is the most basic and core part of the digital system. [0004] ...

AI Technical Summary

Problems solved by technology

However, under the near-threshold voltage, the speed of many computing un

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