182 results about "Cmos fabrication" patented technology

Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and / or buried guard ring structures disclosed in the present application. The introduction of design and / or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.

A compact, integrated LIDAR system utilizes SOI-based opto-electronic components to provide for lower cost and higher reliability as compared to current LIDAR systems. Preferably, an SOI-based LIDAR transmitter and an SOI-based LIDAR receiver (both optical components and electrical components) are integrated within a single module. The various optical and electrical components are formed utilizing portions of the SOI layer and applying well-known CMOS fabrication processes (e.g., patterning, etching, doping), including the formation of additional layer(s) over the SOI layer to provide the required devices. A laser source itself is attached to the SOI arrangement and coupled through an integrated modulation device (such as a Mach-Zehnder interferometer, i.e., MZI) to provide the scanning laser output signal (the scan controlled by, for example, an electrical (encoder) input to the input to the MZI). The return, reflected optical signal is received by a photodetector integrated within the SOI arrangement, where it is thereafter converted into an electrical signal and subjected to various types of signal processing to perform the desired type(s) of signal characterization / signature analysis.

A method for fabrication of silicon-on-nothing (SON) MOSFET using selective etching of Si1−xGex layer, includes preparing a silicon substrate; growing an epitaxial Si1−xGex layer on the silicon substrate; growing an epitaxial thin top silicon layer on the epitaxial Si1−xGex layer; trench etching of the top silicon and Si1−xGex, into the silicon substrate to form a first trench; selectively etching the Si1−xGex layer to remove substantially all of the Si1−xGex to form an air gap; depositing a layer of SiO2 by CVD to fill the first trench; trench etching to from a second trench; selectively etching the remaining Si1−xGex layer; depositing a second layer of SiO2 by CVD to fill the second trench, thereby decoupling a source, a drain and a channel from the substrate; and completing the structure by state-of-the-art CMOS fabrication techniques.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter / buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS / CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.