9 results about "Cmos fabrication" patented technology

Silicon photonics adds optical functionality to electronic integrated circuits allowing leveraging CMOS fabrication processes, integration of CMOS electronics discretely and integration of microelectromechanical systems (MEMS) or Micro-Opto-Electro-Mechanical-Systems (MOEMS) elements. Further, silicon photonics allows hybrid or monolithic integration of semiconductor photodetectors in conjunction with the passive silicon photonics and active elements such as semiconductor optical amplifiers (SOAs). Accordingly, it would be beneficial to provide network designers with silicon photonic optical emitters and transmitters for wavelength division multiplexed networks which can dynamically transmit on one or more channels whilst addressing the inherent issues that silicon photonics and other optical waveguide technologies exhibit for hybrid integration of SOAs and passive photonics.

Single-chip solutions and associated methods that lead to significantly higher capacitance densities than are achievable with current on-chip solutions and that reduce the footprint of a mounting structure. Embodiments of the present invention use vertical stacking to attach one or more discrete embeddable capacitors to an IC chip superstructure or base structure and to establish electrical connections between the discrete embeddable capacitors and the IC chip, either sequentially or simultaneously. The methods according to the invention are compatible with CMOS fabrication temperatures for the IC chip, while allowing the use of capacitors fabricated by other methods that may require significantly higher temperatures. The methods according to the invention enable the connection of relatively large capacitances (e.g.,~0.5 µF - 1 µF) to an IC chip without increasing the two-dimensional area requirement of the IC chip. Some embodiments include reconfigurable discrete / fixed capacitors and / or discrete / fixed capacitors with vias (as opposed to capacitor electrode terminals) for connecting circuits.

A partially completed wafer contains complementary metal–oxide–semiconductor (CMOS) active devices formed with a CMOS fabrication line. Thin-film active devices are formed over the CMOS active devices with a thin-film fabrication line. Wiring between the CMOS active devices and the thin-film active devices may be formed with either or both fabrication lines. Wiring above the thin-film active devices may be formed with the thin-film fabrication line. The thin-film active devices and related wiring provide enhanced functionality to functionality provided by the CMOS active devices.

A structure or PIC structure includes a hybrid plasmonic (HP) waveguide. The HP waveguide includes a waveguide core, and a metal silicide layer contacting the waveguide core. The metal silicide layer replaces noble metals typically provided in hybrid plasmonic waveguides, providing improved optical signal containment characteristics. The metal silicide layer is also compatible with CMOS fabrication techniques, and capable of additional scaling with other CMOS structures. The HP waveguide also has a reduce form factor compared to conventional HP waveguides, providing room for more waveguides closer together.

A fin stack including compressively strained and tensile-strained semiconductor fin regions allows CMOS fabrication to form vertically stacked p-type FinFETs and n-type FinFETs. Aspect ratio trapping within a semiconductor base region within the fin stack provides a relaxed semiconductor base region on which uniaxially strained regions are grown. A dielectric layer may be formed to electrically isolate the compressively strained semiconductor fin region from the tensile-strained semiconductor fin region.

A magnetic device for magnetic random access memory (MRAM), spin torque MRAM, or spin torque oscillator technology is disclosed wherein a magnetic tunnel junction (MTJ) with a sidewall is formed between a bottom electrode and a top electrode. A passivation layer that is a single layer or multilayer comprising one of B, C, or Ge, or an alloy thereof wherein the B, C, and Ge content, respectively, is at least 10 atomic % is formed on the MTJ sidewall to protect the MTJ from reactive species during subsequent processing including deposition of a dielectric layer that electrically isolates the MTJ from adjacent MTJs, and during annealing steps around 400° C. in CMOS fabrication. The single layer is about 3 to 10 Angstroms thick and may be an oxide or nitride of B, C, or Ge. The passivation layer is preferably amorphous to prevent diffusion of reactive oxygen or nitrogen species.

A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source / drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

Disclosed herein are semiconductor devices to provide a CMOS-compatible, wafer-scale, multi-well platform that can be used for biomedical or other applications, and methods to operate the same. In some embodiments, circuitry is provided underneath a multiple-well array to electrically interface with electrodes in the wells. To interface with electrodes in a large array, circuitry may be fabricated on a single silicon (Si) wafer having a dimension that is at least the same or larger than that of the multiple-well array. According to one aspect of the present disclosure, standard CMOS fabrication process such as those known to be used in a standard semiconductor foundry may be used without expensive customization for complex fabrication procedures. This may help the production cost to be lowered in some cases.

Silicon photonics adds optical functionality to electronic integrated circuits allowing leveraging CMOS fabrication processes, integration of CMOS electronics discretely and integration of microelectromechanical systems (MEMS) or Micro-Opto-Electro-Mechanical-Systems (MOEMS) elements. Further, silicon photonics allows hybrid or monolithic integration of semiconductor photodetectors for optical receivers in conjunction with the passive silicon photonics and active elements such as semiconductor optical amplifiers (SOAs) and laser diodes (LDs) for coherent detection receivers for next generation systems. Accordingly, it would be beneficial to provide network designers with silicon photonic receivers for wavelength division multiplexed networks using direct or coherent detection which can dynamically select one or more channels from a large number of incoming channels whilst addressing the inherent issues that silicon photonics and other optical waveguide technologies exhibit such as polarisation dependency.