4 results about "Cmos fabrication" patented technology

Single-chip solutions and associated methods that lead to significantly higher capacitance densities than are achievable with current on-chip solutions and that reduce the footprint of a mounting structure. Embodiments of the present invention use vertical stacking to attach one or more discrete embeddable capacitors to an IC chip superstructure or base structure and to establish electrical connections between the discrete embeddable capacitors and the IC chip, either sequentially or simultaneously. The methods according to the invention are compatible with CMOS fabrication temperatures for the IC chip, while allowing the use of capacitors fabricated by other methods that may require significantly higher temperatures. The methods according to the invention enable the connection of relatively large capacitances (e.g.,~0.5 µF - 1 µF) to an IC chip without increasing the two-dimensional area requirement of the IC chip. Some embodiments include reconfigurable discrete / fixed capacitors and / or discrete / fixed capacitors with vias (as opposed to capacitor electrode terminals) for connecting circuits.

A partially completed wafer contains complementary metal–oxide–semiconductor (CMOS) active devices formed with a CMOS fabrication line. Thin-film active devices are formed over the CMOS active devices with a thin-film fabrication line. Wiring between the CMOS active devices and the thin-film active devices may be formed with either or both fabrication lines. Wiring above the thin-film active devices may be formed with the thin-film fabrication line. The thin-film active devices and related wiring provide enhanced functionality to functionality provided by the CMOS active devices.

Disclosed herein are semiconductor devices to provide a CMOS-compatible, wafer-scale, multi-well platform that can be used for biomedical or other applications, and methods to operate the same. In some embodiments, circuitry is provided underneath a multiple-well array to electrically interface with electrodes in the wells. To interface with electrodes in a large array, circuitry may be fabricated on a single silicon (Si) wafer having a dimension that is at least the same or larger than that of the multiple-well array. According to one aspect of the present disclosure, standard CMOS fabrication process such as those known to be used in a standard semiconductor foundry may be used without expensive customization for complex fabrication procedures. This may help the production cost to be lowered in some cases.

Silicon photonics adds optical functionality to electronic integrated circuits allowing leveraging CMOS fabrication processes, integration of CMOS electronics discretely and integration of microelectromechanical systems (MEMS) or Micro-Opto-Electro-Mechanical-Systems (MOEMS) elements. Further, silicon photonics allows hybrid or monolithic integration of semiconductor photodetectors for optical receivers in conjunction with the passive silicon photonics and active elements such as semiconductor optical amplifiers (SOAs) and laser diodes (LDs) for coherent detection receivers for next generation systems. Accordingly, it would be beneficial to provide network designers with silicon photonic receivers for wavelength division multiplexed networks using direct or coherent detection which can dynamically select one or more channels from a large number of incoming channels whilst addressing the inherent issues that silicon photonics and other optical waveguide technologies exhibit such as polarisation dependency.