179 results about "Cmos fabrication" patented technology

Structures and methods for three-dimensional image sensing using high frequency modulation includes CMOS-implementable sensor structures using differential charge transfer, including such sensors enabling rapid horizontal and slower vertical dimension local charge collection. Wavelength response of such sensors can be altered dynamically by varying gate potentials. Methods for producing such sensor structures on conventional CMOS fabrication facilities include use of “rich” instructions to command the fabrication process to optimize image sensor rather than digital or analog ICs. One detector structure has closely spaced-apart, elongated finger-like structures that rapidly collect charge in the spaced-apart direction and then move collected charge less rapidly in the elongated direction. Detector response is substantially independent of the collection rate in the elongated direction.

Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.

A conventional CMOS fabrication technique is used to integrate the formation of passive optical devices and active electro-optic devices with standard CMOS electrical devices on a common SOI structure. The electrical devices and optical devices share the same surface SOI layer (a relatively thin, single crystal silicon layer), with various required semiconductor layers then formed over the SOI layer. In some instances, a set of process steps may be used to simultaneously form regions in both electrical and optical devices. Advantageously, the same metallization process is used to provide electrical connections to the electrical devices and the active electro-optic devices.

A compact, integrated LIDAR system utilizes SOI-based opto-electronic components to provide for lower cost and higher reliability as compared to current LIDAR systems. Preferably, an SOI-based LIDAR transmitter and an SOI-based LIDAR receiver (both optical components and electrical components) are integrated within a single module. The various optical and electrical components are formed utilizing portions of the SOI layer and applying well-known CMOS fabrication processes (e.g., patterning, etching, doping), including the formation of additional layer(s) over the SOI layer to provide the required devices. A laser source itself is attached to the SOI arrangement and coupled through an integrated modulation device (such as a Mach-Zehnder interferometer, i.e., MZI) to provide the scanning laser output signal (the scan controlled by, for example, an electrical (encoder) input to the input to the MZI). The return, reflected optical signal is received by a photodetector integrated within the SOI arrangement, where it is thereafter converted into an electrical signal and subjected to various types of signal processing to perform the desired type(s) of signal characterization/signature analysis.

A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

An isolation structure and a method of making the same are provided. In one aspect, the method includes the steps of forming a trench in a substrate and forming a first insulating sidewall in the trench and a second insulating in the trench in spaced-apart relation to the first insulating sidewall. A bridge layer is formed between the first and the second sidewalls. The bridge layer, the first and second sidewalls, and the substrate define an air gap in the trench. The isolation structure exhibits a low capacitance in a narrow structure. Scaling is enhanced and the potential for parasitic leakage current due to non-planarity is reduced.

A low power analog linear temperature sensor integrateable with digital and/or analog circuits in CMOS fabrication processes. The sensor is accurately calibrateable at a single temperature that yields a linear relationship between measured differential voltage and temperature over a wide variety of temperature ranges. The sensor provides stable voltage and current references that are essential for wireless sensor platforms. There are many applications where sensors require stable voltage/current references and the physics of the sensor's transduction mechanisms are themselves temperature dependent. Wireless platforms such as, but not limited to, passive RFID tags with the addition of on- or off-chip sensors provide a low cost solution for a variety of low cost sensor applications.

A low loss optical waveguiding structure for silicon-on-insulator (SOI)-based arrangements utilizes a tri-material configuration including a rib/strip waveguide formed of a material with a refractive index less than silicon, but greater than the refractive index of the underlying insulating material. In one arrangement, silicon nitirde may be used. The index mismatch between the silicon surface layer (the SOI layer) and the rib/strip waveguide results in a majority of the optical energy remaining within the SOI layer, thus reducing scattering losses from the rib/strip structure (while the rib/strip allows for guiding along a desired signal path to be followed). Further, since silicon nitirde is an amorphous material without a grain structure, this will also reduce scattering losses. Advantageously, the use of silicon nitride allows for conventional CMOS fabrication processes to be used in forming both passive and active devices.

An optical sensor circuit for generating signals corresponding to received photoelectrons is formed on a single monolithic substrate and includes a charge coupled device (CCD) array. The array is formed of a plurality of pixels constructed by a standard CMOS process. Each pixel is formed of at least one charge well of minority carriers and a gate oxide layer overlaying the at least one charge well. At least two spaced gate electrodes corresponding in position to the at least two charge wells overlays the gate oxide layer. The space between adjacent electrodes defines a gap to transfer charge between adjacent ones of at the least two spaced gate electrodes and the gap is stabilized. A back-illuminated imager is also described in which photocarriers are diverted from devices integrated with the pixel by a PN junction formed in the pixel structure.

A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C³MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. The present invention offers an improved signal to noise ration. The present invention provides for the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. Embodiments of a method for forming transmission lines in an integrated circuit include forming a first layer of electrically conductive material on a substrate. The method includes forming a first layer of insulating material on the first layer of the electrically conductive material. The first layer has a thickness of less than 1.0 micrometers (μm). A transmission line is formed on the first layer of insulating material. The transmission line has a thickness and a width of approximately 1.0 micrometers. A second layer of insulating material is formed on the transmission line. And, a second layer of electrically conductive material is formed on the second layer of insulating material.

A method for fabrication of silicon-on-nothing (SON) MOSFET using selective etching of Si_1-xGe_x layer, includes preparing a silicon substrate; growing an epitaxial Si_1-xGe_x layer on the silicon substrate; growing an epitaxial thin top silicon layer on the epitaxial Si_1-xGe_x layer; trench etching of the top silicon and Si_1-xGe_x, into the silicon substrate to form a first trench; selectively etching the Si_1-xGe_x layer to remove substantially all of the Si_1-xGe_x to form an air gap; depositing a layer of SiO₂ by CVD to fill the first trench; trench etching to from a second trench; selectively etching the remaining Si_1-xGe_x layer; depositing a second layer of SiO₂ by CVD to fill the second trench, thereby decoupling a source, a drain and a channel from the substrate; and completing the structure by state-of-the-art CMOS fabrication techniques.

An ion source for ion implantation system and a method of ion implantation employs a controlled broad, directional electron beam to ionize process gas or vapor, such as decaborane, within an ionization volume by primary electron impact, in CMOS manufacturing and the like. Isolation of the electron gun for producing the energetic electron beam and of the beam dump to which the energetic beam is directed, as well as use of the thermally conductive members for cooling the ionization chamber and the vaporizer, enable use with large molecular species such as decaborane, and other materials which are unstable with temperature. Electron optics systems, facilitate focusing of electrons from an emitting surface to effectively ionize a desired volume of the gas or vapor that is located adjacent the extraction aperture. The components enable retrofit into ion implanters that have used other types of ion sources. Demountable vaporizers, and numerous other important features, realize economies in construction and operation. Achievement of production-worthy operation in respect of very shallow implants is realized.

An optical device for generating narrow-band circularly and elliptically polarized radiation, either by conversion from externally incident light or through thermal emission of heated objects. The optical device includes a metasurface comprised of unit cells, where each unit cell contains structural elements or features that break two mirror inversion symmetries of the unit cell and couple bright and dark resonances. In this manner, the optical device emits circularly polarized radiation that does not exhibit a preference for right-hand circularly polarized light or left-hand circularly polarized light incident upon it. As a result, multiple of such optical devices with different unit cell sizes, geometries and dimensions of the intra-cell elements may be implemented as a tag that thermally emits different states of circularly polarized radiation confined to multiple spectrally-narrow bands. Since the optical device can be fabricated in CMOS, the tag can be used for preventing/identifying tampering with genuine electronic components.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C³MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.