N type SOI lateral double-diffused metal-oxide semiconductor transistor

[0019] Reference figure 2 , An N-type silicon-on-insulator lateral double-diffusion metal oxide semiconductor transistor, comprising: a semiconductor substrate 9, a buried oxide layer 8 is provided on the semiconductor substrate 9, and an N-type doped oxide layer is provided on the buried oxide layer 8. The semiconductor region 7 is provided with a P-well 6 and an N-type drain region 10 on the N-type doped semiconductor region 7, and an N-type source region 11 and a P-type contact region 13 are provided on the P-well 6, and on the surface of the P-well 6 A gate oxide layer 3 is provided, and the gate oxide layer 3 extends from the P well 6 to the N-type doped semiconductor region 7, on the surface of the P-well 6 in the N-type source region 11, the P-type contact region 13 and the area outside the gate oxide layer 3 And the area outside the N-type drain region 10 on the surface of the N-type doped semiconductor region 7 is provided with a field oxide layer 1, and a polysilicon gate 4 is provided on the surface of the gate oxide layer 3 and the polysilicon gate 4 extends to the surface of the field oxide layer 1. The oxide layer 1, the P-type contact region 13, the N-type source region 11, the polysilicon gate 4, and the N-type drain region 10 are provided with an oxide layer 5 on the surface. In the N-type source region 11, the P-type contact region 13, the polysilicon gate 4 and The metal layer 2 is respectively connected to the N-type drain region 10, a first floating oxide layer 121 is provided in the N-type doped semiconductor region 7 and the first floating oxide layer 121 is located under the N-type drain region 10.

[0020] This embodiment also adopts the following technical measures to further improve the performance of the present invention:

[0021] Reference image 3 A second floating oxide layer 122 is provided in the N-type doped semiconductor region 7, and the second floating oxide layer 122 is located under the first floating oxide layer 121.

[0022] The distance between the upper surface of the first floating oxide layer 121 and the lower surface of the N-type drain region 10 is between 0.5 μm and 1 μm.

[0023] The thickness of the first floating oxide layer 121 is between 0.2 μm and 0.5 μm.

[0024] The distance between the second floating oxide layer 122 and the first floating oxide layer 121 does not exceed 0.5 microns.

[0025] The length of the first floating oxide layer 121 is 1 to 1.5 times the width of the drain region 10.

[0026] Although two floating oxide layers are used in this embodiment, in practice, multiple floating oxide layers are allowed to be disposed under the drain region, so that the vertical electric field in the drain region of the device is further optimized, thereby further increasing the breakdown voltage of the device.

[0027] The present invention adopts the following method to prepare:

[0028] 1. To make the required silicon-on-insulator SOI substrate, it can use oxygen injection isolation method, silicon wafer bonding method and other methods (the oxygen injection isolation method is taken as an example below). A dedicated oxygen ion implanter for high beam current can be used to implant oxygen ions into the silicon wafer, and the implant dose is about 1E18/cm 2 , And then perform high temperature annealing at ≥ 1300°C in an inert gas for 3 to 5 hours to form a very thin epitaxial silicon layer and insulating material layer with uniform thickness on the top of the silicon wafer.

[0029] 2. To make the buried oxide layer, it needs a mask to cover the part that does not need to be injected with oxygen atoms, and then use high-concentration oxygen atoms to inject with energy of several megaelectron volts. For the lateral double-diffusion metal oxide semiconductor transistor of high-voltage N-type silicon-on-insulator with only one floating oxide layer structure, only one oxygen atom implantation (1Mev to 2Mev) is required, and then high temperature ≥1300℃ in an inert gas Annealing is performed for 3 to 5 hours to form a continuous oxide layer in the body. For a high-voltage N-type silicon-on-insulator lateral double-diffused metal oxide semiconductor transistor with two or more floating oxide layers, it needs to be performed twice or For multiple implantation of oxygen atoms, pay attention to the difference in energy of two or more implants (the first time is 3Mev to 4Mev, and the second time is 1Mev to 2Mev). Then high-temperature annealing is carried out, and then the silicon wafer is thinned and flattened to reach the required thickness.

[0030] 3. It is the production of conventional lateral double diffused metal oxide semiconductor transistors, which includes P-type well implantation, field oxygen preparation, gate oxide growth, etching, polysilicon deposition and etching, and then high-concentration source and drain The injection area and the substrate contact the injection area preparation, and finally the lead hole, aluminum lead preparation and passivation treatment.