Image sensor package with grain receiving opening and method of the same
A technology of image sensor and crystal grain, which can be used in electric solid-state devices, semiconductor devices, radiation control devices, etc., and can solve problems such as increased thickness
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[0040] figure 1 To illustrate a cross-sectional view of a CIS-CSP (CMOS Image Sensor Chip Scale Package) according to an embodiment of the present invention; figure 1 As shown, the structure of the PLP includes a substrate 2 having predetermined die vias 10 and pad (interconnect) vias 6 formed therein to accommodate a die 16; die 16 is preferably an image sensor die A plurality of pad via holes 6 are formed to connect the upper surface and the lower surface of the substrate 2, wherein the pad (interconnection) via holes 6 are surrounded by the substrate 2; a conductive material will be filled into the via holes 6 to conduct The (terminal) pad 8 is positioned on the lower surface of the substrate 2 and is connected to the pad through hole 6 with the conductive material; the conductive wire pad 22 (such as a metal material) is positioned on the upper surface of the substrate 2 and connected to the pad through hole 6. The conductive material is also connected to the pad through ...
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