Wafer three-dimensional integrated lead wire process for three-dimensional memory and structure thereof

A technology of integrated leads and three-dimensional storage, which is applied in the manufacture of electric solid-state devices, semiconductor devices, semiconductor/solid-state devices, etc., can solve problems such as difficulties in leading out the first metal layer, achieve the effects of reducing production costs and improving product yields

Active Publication Date: 2018-01-30
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

When the above-mentioned wafer three-dimensional integrated wiring process is applied to three-dimensional memory technology, such as figure 2 As shown, since the three-dimensional memory unit is fabricated vertica

Method used

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  • Wafer three-dimensional integrated lead wire process for three-dimensional memory and structure thereof
  • Wafer three-dimensional integrated lead wire process for three-dimensional memory and structure thereof
  • Wafer three-dimensional integrated lead wire process for three-dimensional memory and structure thereof

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Embodiment 1

[0041] refer to Figure 3-8 As shown, Embodiment 1 of the present invention provides a wafer three-dimensional integrated wiring process, including the following steps:

[0042] A first wafer 11 is provided, the first wafer 11 has a front side and a back side arranged oppositely, and a contact hole area 12 is provided on at least a part of the front side of the first wafer 11;

[0043] A dielectric layer 13 is formed in the contact hole region 12, the dielectric layer 13 is an oxide dielectric layer 13 or a nitride dielectric layer 13, and the process of forming the dielectric layer 13 in the contact hole region 12 includes lithography, etching, deposition , one of filling and grinding or any combination thereof, the dielectric layer has a top surface and a bottom surface oppositely arranged, wherein the top surface is the side facing the front side of the first wafer, and the bottom surface is the side facing the back side of the first wafer side;

[0044] A semiconductor dev...

Embodiment 2

[0053] In this embodiment, the parts different from the above embodiments will be described, and the same parts will not be repeated.

[0054] refer to image 3 As shown, the dielectric layer 13 has a bottom surface and a top surface oppositely disposed, and the bottom surface is a side farther away from the first metal layer 18 than the top surface. In the step of forming the dielectric layer 13, at first, a shallow trench is formed in the contact hole region 12 on the front surface of the first wafer 11 by lithography and etching processes, and then a shallow trench is formed in the shallow trench by deposition and filling processes. The dielectric layer 13 is formed in the groove, and the dielectric layer 13 may be ground to be planarized by a grinding process later. After the above process steps, the bottom surface of the formed dielectric layer 13 is located inside the first wafer 11 , and the top surface of the dielectric layer 13 is flush with the front surface of the ...

Embodiment 3

[0064] In this embodiment, the parts different from the above embodiments will be described, and the same parts will not be repeated.

[0065] The dielectric layer 13 has a bottom surface and a top surface opposite to each other, and the bottom surface is a side farther away from the first metal layer 18 than the top surface. In the step of forming the dielectric layer 13, at first, a shallow trench is formed in the contact hole region 12 on the front surface of the first wafer 11 by lithography and etching processes, and then a shallow trench is formed in the shallow trench by deposition and filling processes. The dielectric layer 13 is formed in the groove, and the dielectric layer 13 may be ground to be planarized by a grinding process later. After the above process steps, the bottom surface of the formed dielectric layer 13 is located inside the first wafer 11 , and the top surface of the dielectric layer 13 is higher than the front surface of the first wafer 11 .

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Abstract

The invention provides a wafer three-dimensional integrated lead wire process and a structure thereof. The process can be applied to a wafer three-dimensional integration process for the wafers of a three-dimensional memory. A dielectric layer 13 is arranged between a first wafer 11 and a three-dimensional memory device 14 and a contact hole 15 for metal interconnection is configured to be in contact with the dielectric layer 13. The invention provides a new lead wire process, making it possible to pass through a thick device layer for wire leading on a backside.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a wafer three-dimensional integration lead process and its structure, which can be applied to the wafer three-dimensional integration process of a three-dimensional memory wafer. Background technique [0002] The continuous shrinkage of semiconductor integrated circuit devices has continuously improved the integration level. At present, more than 1 billion transistors can be integrated on a chip area per square centimeter, and the total length of metal interconnection lines has reached tens of kilometers. This not only makes the wiring extremely complicated, but more importantly, the delay, power consumption, and noise of the metal interconnection increase with the reduction of the feature size, especially the RC (resistor-capacitor) delay of the global interconnection, which seriously affects performance of integrated circuits. As a result, metal interconnec...

Claims

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Application Information

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IPC IPC(8): H01L21/768H01L23/48
CPCH01L21/76898H01L23/481H01L2224/05
Inventor 朱继锋陈俊胡思平吕震宇
Owner YANGTZE MEMORY TECH CO LTD
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