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System, apparatus, and method for modifying the order of memory accesses

A memory and memory word technology, applied in the field of computer systems, can solve problems such as wasting available memory bandwidth

Active Publication Date: 2010-10-13
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since DRAM typically has multiple banks that cycle independently, this bank timing conflict wastes available memory bandwidth

Method used

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  • System, apparatus, and method for modifying the order of memory accesses
  • System, apparatus, and method for modifying the order of memory accesses
  • System, apparatus, and method for modifying the order of memory accesses

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Embodiment Construction

[0023] Embodiments disclosed herein include apparatus and methods for producing improved memory performance in a multi-threaded and multi-processor system environment.

[0024] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the invention, but it is to be understood that other embodiments may be utilized and structural, logical, and electrical changes may be made within the scope of the invention.

[0025] In this description, circuits and functions may be shown in block diagram form in order not to obscure the invention in unnecessary detail. Furthermore, the specific circuit implementation shown and described is an example only, and unless otherwise specified herein, should not be considered the only w...

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Abstract

Systems and methods for controlling memory access operation are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a destination bank, and the request is placed in an appropriate bank queue. An ordering unit determines if the current request can be reordered relative to the received order and generates a new memory cycle order based on the reordering determination. The reordering may be based on whether there are multiple requests to the same memory page, multiple reads, or multiple writes. A memory interface executes each memory request in the memory cycle order. A data buffer holds write data until it is written to the memory and read data until it is returned to the requestor. The data buffer also may hold memory words used in read-modify- write operations.

Description

[0001] Related Application Cross Reference [0002] This application claims that the name of the application filed on November 15, 2007 is "System, Apparatus, and Method for Modifying the Order of Memory Accesses (system, device and method for modifying the order of memory access)", and the serial number is 11 / 940,745 U.S. patent application filing date benefits. technical field [0003] Embodiments relate to computer systems, and more particularly to methods of operation of memory controllers to increase memory access efficiency. Background technique [0004] In most computers and data processing systems, the main active memory, which is usually Random Access Memory (RAM), is Dynamic Random Access Memory (DRAM). The structure of DRAM usually consists of several memory cells organized into several banks. Each bank corresponds to an array of memory cells, where each cell is correspondingly associated with a data number (eg, bit) at a memory address. In particular, memory...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/00G06F9/00
CPCG06F9/3834G06F13/1631G06F9/3004G06F13/1673G06F9/30087
Inventor 戴维·R·雷斯尼克
Owner MICRON TECH INC
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