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362 results about "IOPS" patented technology

Input/output operations per second (IOPS, pronounced eye-ops) is an input/output performance measurement used to characterize computer storage devices like hard disk drives (HDD), solid state drives (SSD), and storage area networks (SAN). Like benchmarks, IOPS numbers published by storage device manufacturers do not directly relate to real-world application performance.

Shared I/O ports for multi-core designs

The present invention provides a shared I / O port and a configurable interconnect allowing any of a plurality of cores to access any pin of a shared I / O port. Preferably, one of the plurality of cores is designated as a master core at least with respect to the configuration of the shared I / O port(s), and the remaining cores desiring to gain access to the shared I / O port(s) are designated as non-master or slave cores. It is the responsibility of the master core to reassign chip resources such as the shared I / O port(s) for use by either the master core or by any of the shared cores. Preferably, all shared I / O ports are controlled by default by the master core. The slave cores communicate with the master core through a suitable internal messaging system. If a slave core requires use of a particular I / O pin or I / O port not already configured appropriately for its use, the slave core will send an appropriate message to the master core through the messaging system, e.g., a dual port memory mailbox. Preferably, the master core will then pass a message back to the requesting slave core indicating completion of the requested reconfiguration. The master core preferably keeps track of which core currently has control of each I / O pin or port using appropriate internal registers. The master core communicates with the relevant I / O pin or port using its I / O data bus, while the slave core communicates with the relevant I / O pin or port using its I / O data bus. IOP configuration signals from the master core configure and thus determine which core in the multi-core integrated circuit or hybrid circuit has access to I / O control modules or registers to control the direction, mode, interrupt generation capability, and / or status of the shared I / O port(s).
Owner:LUCENT TECH INC

Realizing method and system for NVME protocol multi-command queues

ActiveCN104536701AThe number of command queues is smallThe number of command queues is largeInput/output to record carriersIOPSQueue number
The invention discloses a realizing method for NVME protocol multi-command queues. The method includes the steps that commands and queue information of the command queues are stored separately; uniform command storage caches are set to store the concrete commands corresponding to elements of all the command queues and queue numbers corresponding to the commands; a queue information table is set to store the queue information of all the queues existing at the Host end at present; when an SSD controller executes the concrete commands according to the sequence, the corresponding queue information is searched for from the queue information table according to the queue numbers corresponding to the concrete commands. The invention discloses a realizing system for the NVME protocol multi-command queues. As the commands are actively read from the command queues at the Host end, the uniform command storage areas are opened up in the controller to store the commands, and the command queue information is obtained by searching the table when the commands are executed; the realizing method has the advantages that few storage resources are consumed when one item of command queue support is added to a control chip, a large number of command queues can be supported, and IOPS can be improved greatly.
Owner:RAMAXEL TECH SHENZHEN
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