Management system and method of processor last level high-speed buffer

Abstract

The invention discloses a management system and a method of processor last level high-speed buffer. The management system of the processor last level high-speed buffer comprises recording a couple of an access block and a discharge block every time when a last level buffer fails to access by a gigabyte (GB) monitor, switching a replacement pattern or a bypass pattern by studying behavior guide of an optimal bypass algorithm, wherein action of the optimal bypass algorithm is formed through actions of selection and adoption of a replacement method and a bypass method according to conditions of the optimal bypass algorithm occurred in follow-up access of the last level high-speed buffer in an accumulation mode; judging a first condition which satisfies the optimal bypass algorithm according to an access block tag and a discharge block tag of a present record in once occurrence of failure of the last level high-speed buffer, and adopting the replacement method when reusable distance of the access block is smaller than the reusable distance of the discharge block, and otherwise, adopting the bypass method. Bypass and replacement are treated as the same strategy to be switched in the management system and the method of the processor last level high-speed buffer.

Description

technical field [0001] The invention relates to modern processor technology, in particular to a management system and method of the last level cache in the processor. Background technique [0002] Power consumption has become a key limiting factor for scaling single-core and multi-core processors, and the last-level cache has been proven to effectively increase performance while using less power. Therefore, a larger last-level cache will appear in future processors. The management strategy of the last-level cache can significantly affect its hit ratio, so it is crucial to the performance of the cache. [0003] In the last-level cache, because the reuse distance of a large number of cache blocks is greater than the capacity of the cache, the commonly used least recently used algorithm (LRU, Least Recently Use) and its approximate algorithm perform poorly. There have been a lot of algorithm researches trying to capture the access of these long-distance reused blocks to manag...

AI Technical Summary

Problems solved by technology

[0009] The above methods either have limited performance improvement, or require a large amount of storage overhead and hardware changes to achieve

Some even need to get information such as PC that is difficult to get in the last level cache, so it is difficult to achieve

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