Scalable high performance 3d graphics

Abstract

A high-speed ring topology. In one embodiment, two base chip types are required: a "drawing" chip, LoopDraw, and an "interface" chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Description

[0001] This application claims priority under 35 U.S.C. .sctn.119(e) from U.S. Provisional Application Serial Number 60 / 367,064, filed Mar. 22, 2002, which is herein incorporated by reference in its entirety.[0002] 1. Field of the Invention[0003] This invention relates to the field of computer graphics, specifically 3d graphics hardware accelerators.[0004] 2. Description of the Related Art[0005] Most conventional general purpose computers have some form of hardware sub-system that can couple information stored or computed within the computer to some form of physical image display devices as interactive visual feed-back to the human user(s). While decades ago these physical image display devices and the special electronics that coupled the computer to them were very primitive, e.g., blinking lights, "glass ttys", or oscilloscopes, over time the sophistication has grown to the point where the hardware sub-system, or graphics system dedicated to driving the physical image display devic...

AI Technical Summary

Problems solved by technology

While decades ago these physical image display devices and the special electronics that coupled the computer to them were very primitive, e.g., blinking lights, "glass ttys", or oscilloscopes, over time the sophistication has grown to the point where the hardware sub-system, or graphics system dedicated to driving the physical image display devices are quite complex, specialized computational systems in their own right.

These systems also support only the most limited forms of antialiasing filtering of these samples during video output signal generation.

Conventional 3d graphics hardware accelerators for real-time interaction have only just started to provide very limited support for programmable shading.

The most sophisticated 3d graphics hardware accelerator chip on the market today can only support eight instruction steps at the most important point in the graphics pipeline, the pixel shader, and do not allow any conditional instruction steps.

This is nowhere near sufficient to give end-users the flexibility and quality they want.

These multiple interconnects or busses are expensive to build, both in the cost of incremental pins on the chip's package, the cost of wires and connectors on the printed circuit boards, and in the cost of designing and testing several different custom crafted interconnect bus protocols.

Thus, much of the full aggregate bandwidth of these interconnects or buses is rarely if ever used, and potentially represents wasted product engineering and / or product costs.

The current middle range of the 3d graphics accelerator market is still somewhat price sensitive, but is also more feature and performance sensitive.

The resulting systems usually require several different expensive asics to be designed and fabricated.

These systems also generally produce just one product configuration; typically it is not possible to take the same asics (with no changes) and build a more expensive but faster product, or a slower but less expensive product.

Additionally, while frame buffer storage that can't be written into with a pixel fill rate of 6.times. the video output signal video format pixel rate and read out at the same 6.times. rate is still unusable as storage, it is not unusable for texture storage.

This processing may result in pixels and other data that need to be sent to the (distributed) frame buffer.

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