52 results about "Endianness" patented technology

A memory system can store data in either a big endian mode or a little endian mode. Memory accessing logic 810 utilises byte invariant addressing to retrieve multiple data elements from that memory to be stored within a SIMD register 812. Data element reordering logic 808 is responsive to an endianess mode specifying signal and a data element size specifying signal to reorder retrieved bytes such that the data elements when stored within the SIMD registers 812 are invariant irrespective of the endianess mode being used by the memory.

A method is described for changing the order of bytes of digital signals transmitted in frames according to a cyclic rotation of the bytes and for changing the frame format. This method can advantageously be used in concatenated coding scheme to achieve the best trade off between coding gain and line bit rate.

The data sharing apparatus in the present invention includes a first processor 10 and a second processor 20, each of a different endianness, that are both connected to the memory via the data bus, in a byte order based on the endianness of the first processor 10. It also includes an address conversion unit 21 which converts at least one lower bit of an address to indicate a reversed position of data in the data bus, and outputs the converted address to the memory, in the case where the second processor 20 performs a memory access on the shared memory for data with a smaller width than the data bus.

A data processing engine is provided, which includes an endian register, an endian control device, and a byte swapper. The endian register stores a plurality of endian control bits. Each endian control bit indicates the default data endianness of a type of address space accessible to the data processing engine. Each endian control bit is in either a big-endian state or a little-endian state. The endian control device is coupled to the endian register. The endian control device provides an endian signal according to the endian control bits and the instruction executed by the data processing engine. The endian signal is in either the big-endian state or the little-endian state. The byte swapper is coupled to the endian control device. The byte swapper transmits data and changes the byte order of the data when the byte order of the data is inconsistent with the state of the endian signal.

Apparatus and methods describe herein, for example, a process that can include receiving a potentially malicious file, and dividing the potentially malicious file into a set of byte windows. The process can include calculating at least one attribute associated with each byte window from the set of byte windows for the potentially malicious file. In such an instance, the at least one attribute is not dependent on an order of bytes in the potentially malicious file. The process can further include identifying a probability that the potentially malicious file is malicious, based at least in part on the at least one attribute and a trained threat model.

A method and system for processing high definition video data to be transmitted over a wireless medium is disclosed. In one embodiment, the method includes receiving an information packet having the length of L bytes, wherein L=(MOEOE)+A, and where: M is the depth of an interleaver, n is the number of interleavers, K is an encoding code length and A is the number of remainder bytes with respect to MOEOE bytes, wherein the remainder bytes are located at the end of the information packet. MOEOE bytes represent MOE codewords, wherein the remainder bytes sequentially form a plurality of remaindercodewords, and wherein the plurality of remainder codewords comprise a last codeword which is located at the end of the remainder codewords. The method further includes i) shortening the last codeword such that the resultant shortened codeword is shorter in length than each of the remaining codewords of the information packet and ii) adding dummy bits to the outer encoded data so as to meet a predefined size requirement for an outer interleaver.

A system and method for decoding an unknown automotive controller area network (“CAN”) message definitions. CAN data vehicle signal mappings are typically held in secret and varied by automotive model and year. Without knowledge of the mappings, the wealth of real-time vehicle data hidden in the automotive CAN packets is uninterpretable—impeding research, after-market tuning, efficiency and performance monitoring, fault diagnosis, and privacy-related technologies. This technology can ascertain the CAN signals' boundaries (start bit and length), endianness (byte ordering), signedness (binary-to-integer encoding) from raw CAN data. This allows conversion of CAN data to time series. Interpreting the translated CAN data's physical meaning and finding a linear mapping to standard units (e.g., knowing the signal is speed and scaling values to represent units of miles per hour) can be achieved for many signals by leveraging diagnostic standards to obtain real-time measurements of in-vehicle systems. The system and method can be integrated into lightweight hardware enabling an OBD-II plugin for real-time in-vehicle CAN decoding or run on standard computers. The system can output a standard DBC file with the signal definition information.

The invention discloses a byte order adjustment method in binary translation, belonging to the technical field of computers, which comprises the following steps: loading a source program executable image by the execution engine of a dynamic binary translation system, adjusting the byte orders of the contents of each program segment, and synchronously adjusting the number of loaded parameters, contents of the parameters and environmental variables; modifying the effective address of an intermediate command representing internal memory access so that the expression of the modified effective address accords with the semantic of the internal memory access of a source program so as to load or store correct data in an internal memory; translating the source program command into the intermediate command by a front decoder, adding the generated intermediate command to a constructed intermediate command basic block until the occurrence of direct skip or system call, finishing the construction of the current basic block, and sending the basic block to a back end for executing. The invention avoids the flitting of byte orders of internal memory data by using the method for modifying internal memory address, has high efficiency, correctness and commonality in the field of binary translation.

Methods, software/firmware, and apparatus to support use of software running on platform hardware employing different endianness. In one embodiment, an endian byte order shim is implemented in a firmware stack to facilitate the use of software running on a computer platform having a processor employing an endianness that is different from the endianness native to the software. In response to software calls into the firmware, the endian byte order shim converts the endian byte order of the call arguments, as necessary, and passes the converted arguments to the firmware. Similarly, return arguments generated via the firmware (and/or platform hardware) are converted back to the endian byte order native to the software prior to being returned to the software.

Embedding endianness information within data and sending and receiving data with the embedded endianness information. Data may be contained in a data structure. To embed endianness information in a data structure, unused bits in a data structure are identified. A number of the unused bits are then selected based on the possible unpacking combinations of the data structure. The endian bit values are set to a pattern to indicate the endianness of the data structure. Data that has been packed by a transmitting module can be unpacked by a receiving module based on the detected endian bits. An algorithm may be used to determine which unused bits to select as the endian bits.

Presented herein are systems and methods for pixel reordering and selection. A decoded frame is stored in a frame buffer with a particular pixel order and byte order. A pixel feeder fetches portions of the decoded frame and stores portions of the frame in a double buffer with the same pixel order and byte order. An endian swizzle converts the byte ordering to a predetermined format, as needed. Reordering logic changes the pixel order to a predetermined order. Selection logic selects luma and chroma pixels from fetched pixels and provides the luma pixels to a luma pixel register, chroma Cr pixels to a chroma Cr pixel register, and chroma Cb pixels to a chroma Cb pixel register.

A data processing apparatus and a data processing method include reading order information included in a data file according to one of a pair of byte orders, comparing the read order information with preset reference information, and decoding the data file if the order information is equal to the reference information.

The IEEE1394 bus communication protocol has three layers: physical layer, link layer, and transaction layer. A link layer IC implements the interface to an external application and prepares data for sending on the bus, or interprets incoming data packets from the IEEE1394 bus. A physical layer IC implements the direct electrical connection to the bus and controls many functions including arbitration for sending data on the bus. A problem exists due to the fact that the header data of the IEEE1394 asynchronous data packets consists of 32 bit words which have to be interpreted as 32 bit words in the connected application data processing unit (30). The IEEE1394 bus interface unit (20) is defined to be of big endian type. In a little endian type application data processor (30) the data word order can only be correctly interpreted after a byte order change. According to the invention the byte order change is performed in the data link layer unit (21) automatically with hardware circuitry for asynchronous data packets.

The invention provides a method for solving an unknown positive integer on the basis of a congruence theory of the positive integer, and builds an encryption and decryption method for information storage and extraction in a distributed cache. The method comprises the steps of firstly converting data D into a matrix with N rows and n columns according to a byte order, defining a pairwise coprime integer set and constructing a unary linear congruence equation set by original data and the defined integer set according to the congruence theory; solving a solution, transforming the solution into a matrix and converting the matrix into data columns according to the scheme of constructing the matrix according to the original data, namely obtaining a ciphertext; and constructing a matrix by using the ciphertext during decoding, reversely solving congruence equations to obtain the matrix of the original data and reconstructing original data columns.

An arrangement for transmitting independent serial data streams through synchronous Time Division Multiplexing (TDM) switches with a number of input and output lines is disclosed. At the receiving side of a switch, there is one data buffer per TDM bus buffering the data before transfer on the bus. A connection table associated with each buffer includes entries addressing the bytes in the buffer. The order of the addresses determines the order of the bytes as they are transferred over the bus. Also, at the transmitting side, there is one data buffer per bus, but only one common connection table. The connection table is divided into one memory area per output line, and determines the order of the data bytes, as they will occur at the respective output lines.

An embodiment of the invention includes code, such as a compiler, that enables byte order dependent code to execute on opposite byte order dependent architectures or systems. The compiler analyzes source code and produces diagnostic reports that indicate where source code changes are desirable to produce 'endian neutral' source code versions that are compatible with opposite byte order dependent architectures or systems. Such source code changes may be desirable for code portions that will produce implicit byte order changes or byte order border crossings. The modified source code that is generated may include the semantics of the desired endian conversion, as opposed to generated executable code that includes proper endian formats but which may limit the architectures to which the code is applicable.

Presented herein are systems and methods for pixel reordering and selection. A decoded picture is stored in a frame buffer with a particular pixel order and byte order. A input data write unit fetches portions of the decoded picture and stores portions of the picture in a double buffer with the same pixel order and byte order. An endian swizzle converts the byte ordering to a predetermined format, as needed. Reordering logic changes the pixel order to a predetermined order. Selection logic selects luma and chroma pixels from fetched pixels and provides the luma pixels to a luma pixel register, chroma Cr pixels to a chroma Cr pixel register, and chroma Cb pixels to a chroma Cb pixel register.