Data sharing apparatus and processor for sharing data between processors of different endianness

Abstract

The data sharing apparatus in the present invention includes a first processor 10 and a second processor 20, each of a different endianness, that are both connected to the memory via the data bus, in a byte order based on the endianness of the first processor 10. It also includes an address conversion unit 21 which converts at least one lower bit of an address to indicate a reversed position of data in the data bus, and outputs the converted address to the memory, in the case where the second processor 20 performs a memory access on the shared memory for data with a smaller width than the data bus.

Description

[0001] (1) Field of the Invention[0002] The present invention relates to a data sharing apparatus containing a memory and two processors of different endianness, as well as such processors for the apparatus, and particularly to data sharing between processors.[0003] (2) Description of the Related Art[0004] In the case where the basic word length of a processor is 2 bytes (16 bits) or more, there are two formats for byte ordering in storing data of 2 bytes or more into a memory, the so-called "big-endian" and "little-endian". This is because the basic word length has 2 bytes or more, as opposed to the byte units in which addresses are assigned in a memory.[0005] First, the big-endian format shall be explained.[0006] Big-endian is a format for the ordering of a byte sequence (byte order) during the storage of data of 2 bytes or more, into a memory having byte unit addresses. It refers to the format that stores data in an ascending order of memory addresses, beginning with the byte at ...

AI Technical Summary

Benefits of technology

[0025] According to this structure, since the first processor and the second processor access the memory in the same byte order for data with the same width as the data bus, the sharing of data with the same width as the data bus through an extremely simple structure is realized as an effect of the present invention. In addition, through the address conversion unit, it becomes possible for the processor to access the memory for data with a smaller width than the data bus. Furthermore, since the processor can be realized through simple hardware such as the address conversion unit, it does not become an impediment to memory access speed.

[0045] Furthermore, in addition to (A) and (B), (C) by defining variables which are shorter than the basic word length, in reversed orders within the basic word length, in structure definition within application programs for the first processor and the second processor, data can be shared by the little-endian-type first processor and the big-endian-type second processor, not only through access of the shared memory in word units, but also through access in half-word and byte units Also, in addition to (A) and (B), since during (D) DMA transfer, the same address conversion in (B) is used, data of different endianness is performed of DMA transfer, and data sharing for the source and destination through half-word unit and byte unit access becomes possible.

Problems solved by technology

Moreover, since delays arise due to endian conversion, the technology poses a barrier to high speed memory access, even carrying with it the problem of hindering the speed of other processors, in the case where data is shared.

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