16-bit FEC decoding realization method for gpon

An implementation method and codeword technology, applied in the direction of using linear codes for error correction/detection, using block codes for error correction/detection, cyclic codes, etc.

Inactive Publication Date: 2010-03-17
HANGZHOU DIANZI UNIV +1
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Problems solved by technology

[0007] The purpose of the present invention is to provide a 16-bit FEC decoding implementation method applied to GPON in order to solve the short byte problem of FEC decoding application in GPON

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  • 16-bit FEC decoding realization method for gpon
  • 16-bit FEC decoding realization method for gpon
  • 16-bit FEC decoding realization method for gpon

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Embodiment Construction

[0045] A 16-bit FEC decoding implementation method applied to GPON, comprising the steps:

[0046] Step (1). Receive the RS code, and let the RS code speed up through the asynchronous FIFO;

[0047] The present invention uses an asynchronous FIFO to temporarily store the incoming 120-byte valid data. Because GPON downlink frames are continuously transmitted, that is, each downlink frame will encounter this short byte problem when decoding FEC, so in order to avoid the accumulation of data in this FIFO, the output clock of FIFO must be increased. If the input system clock adopts x megahertz, then the output clock must be greater than or equal to y=(135x / 120) megahertz, then a clock of y megahertz must be used for subsequent FEC decoding. After such a speed-up, the insertion time of 135 zeros can be less than or equal to the time for storing 120 bytes into the FIFO, that is, the data stored in the FIFO will not exceed 120 bytes. After the data is restored to normal reading, th...

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Abstract

The invention relates to a 16-bit FEC decoding realization method for GPON. The prior art can not realize the 16-bit FEC decoding. The 16-bit FEC decoding realization method comprises the following steps: firstly, receiving a RS code and conducing asynchronous FIFO speed acceleration on the RS code; secondly, solving a syndrome of the RS code after the speed acceleration, and then applying the solved syndrome to an improved Euclidean algorithm to solve a polynomial of an error position and an error value; and finally using a Chien search algorithm for searching the error position, using a Forney algorithm for computing the error value, and obtaining a correct value through conducing XOR on the error value and a value received on the error position, thus completing decoding error-correctionprocess. The decoding realization method respectively adopts three paths for parallel computing when using an MEA algorithm, thus shortening the time of the MEA computing; and simultaneously, two Chien search and Forney algorithm are respectively used, thus resolving the problems existing in the 16-bit RS decoding when only one Chien search and Forney algorithm module is used.

Description

technical field [0001] The invention belongs to the field of G-bit passive optical network, and specifically relates to a 16-bit FEC decoding realization method applied to GPON. Background technique [0002] GPON (Gigabit-Capable PON, G bit passive optical network) technology is the latest generation of broadband access standard based on the ITU-TG.984.x standard, which has many advantages such as high bandwidth, high efficiency, large coverage, and rich user interfaces. , is regarded by most operators as an ideal technology to achieve broadband and comprehensive transformation of access network services. ONU is the user end of GPON. Based on the 2.5Gbit / s downstream rate of GPON, the receiving end of the downstream ONU needs to implement 16-bit FEC decoding. [0003] The FEC decoding in GPON adopts the RS (255, 239) decoding method, which uses four steps to decode: Step 1 finds the adjoint formula; Step 2 solves the error position polynomial and error value polynomial; Ste...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/15
Inventor 陈科明庄世辉洪爱金马琪潘剑侠胡睿尹法纪王晓晖
Owner HANGZHOU DIANZI UNIV
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