Logical unit multiplexing system

Abstract

The invention discloses a logical unit multiplexing system which is applicable to an error correction technology of a solid-state hard disk. The logical unit multiplexing system comprises a coding circuit and a decoding circuit. The logical unit multiplexing system is characterized in that: the coding circuit comprises a linear feedback shifting register which is used for complementing a coded / decoded information polynomial; the decoding circuit comprises a syndrome calculating module, a key equation determining module and a Chien search module; the syndrome calculating module is used for calculating to acquire a syndrome and comprises a syndrome calculating module and the linear feedback shifting register; the coding circuit and the decoding circuit multiplex the linear feedback shifting register in a time sharing mode; the key equation determining module is used for determining a key equation according to the syndrome; and the Chien search module is used for judging to acquire a root of the key equation and outputting error position information according to the root of the key equation. Therefore, a logical unit can be multiplexed in the time sharing mode, the area of an error correction code (ECC) chip can be effectively reduced, the power consumption of the ECC chip is reduced, and cost is saved.

Description

technical field [0001] The invention relates to the error correction technology of the solid state disk, in particular to a logic unit multiplexing system applied to the error correction technology of the solid state disk. Background technique [0002] At present, the error correction technology applied to solid-state hard drives is mainly BCH. The encoding process is realized by a linear feedback shift register (LFSR). The decoding process is divided into three parts. The first is the calculation of the adjoint formula. The finite field multiplier implementation is followed by the key equation solving and finally the money search procedure. [0003] Both the adjoint calculation modules of the encoding process and the decoding process need to be implemented using linear feedback shift registers. Both are mathematical remainders of polynomials. The difference lies in the difference between the divisor and the dividend. In terms of hardware, there are overlaps . In addition ...

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Problems solved by technology

[0005] In summary, the existing solid-state hard disk error correction chip obviously has inconvenience and defects in actual use, so it is necessary to improve it

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