RS (reed Solomon) decoding method and device thereof in communication system

Abstract

The invention relates to the communication technology and discloses an RS (reed Solomon) decoding method and device thereof in the communication system. By serial decomposition calculation of common parallel iBM algorithm, hardware resource required for solving key equations is greatly reduced and path delay is reduced under the condition of no influence on continuous decoding. Also, by combining and optimizing Chien search and Forney algorithm process, that is, odd-even terms in error position polynomial terminals and error value polynomial terms are split, and control logic and repeated calculation is reduced. Therefore, consumption of the hardware resource is only 1 / 2 to 1 / 3 of that of the common iBM algorithm, the maximum clock frequency and effective data bandwidth are improved by about 30%, high-speed channel error technology can be applied on a low-density chip, and cost is reduced.

Description

technical field [0001] The invention relates to communication technology, in particular to an RS decoding method and a device thereof in a communication system. Background technique [0002] Reed-Solomon Code (referred to as "RS CODE") is a non-binary coding method with very strong error correction capability, which is applied to channel error correction. Reed-Solomon Decoding (Reed-Solomon Decode, referred to as "RS DECODE") is to perform RS decoding on encoded data, and complete error detection, error finding and error correction in data packets through a series of operations. Erroneous data are corrected. Finite field (GF Field) is the number field of linear block codes, which is a cyclic group field applied in channel coding and cryptography, and RS coding and decoding is a special coding and decoding method defined in finite fields. [0003] Field-Programmable Gate Array (Field-Programmable Gate Array, referred to as "FPGA") is a product of further development on the ...

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Problems solved by technology

[0005] However, the inventors of the present invention have found that the disadvantages of the above method are: 1) Eculid and its variant algorithms involve polynomial order comparison and coefficient exchange. Although the RS decoding speed of this algorithm is very fast, it is extremely consuming resources, not suitable for low-density FPGA chips

2) The ordinary iBM algorithm uses a multiply-add tree structure when solving key equations, and the path delay is relatively large

Although the ordinary iBM algorithm can solve the key equations in a very short clock cycle, it consumes a lot of finite field adders and finite field multipliers, and the resource consumption is not fast enough.

3) Several sets of calculation units of the RiBM algorithm share a set of control signals, which will cause the wiring of this set of control signals to be too long when implemented in FPGA, which is not conducive to the improvement of decoding speed, and the RiBM algorithm occupies a lot of resources

4) The money search and Forney algorithms are calculated independently, and each requires a set of control logic to cause waste of resources

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