31results about How to "Reduce control logic" patented technology

The invention provides a maximum-power-point global scanning method, an inverter and a photovoltaic system. The maximum-power-point global scanning method includes: firstly, judging whether global scanning is needed or not; secondly, when global scanning is needed, subjecting busbar voltage of the inverter in the photovoltaic system to judgment, maximum-power-point scanning and processing; thirdly, processing operating states of DC (direct current) / DC converters; fourthly, subjecting multi-channel PV input to maximum-power-point global scanning so as to find a maximum power point of each PV array; finally, after maximum-power-point global scanning is terminated, subjecting the multi-channel PV input of the inverter to normal MPPT (maximum power point tracking) scanning. By the maximum-power-point global scanning method, the problem that global scanning of multi-channel PV input of an inverter lacks in the prior art is solved, generating capacity is increased and system control logic is reduced.

The present application provides a lubricating oil valve controlled by external air, which includes: a valve housing with a housing chamber, a lubricating oil inlet at its side, and a lubricating oil outlet at its lower end, the lubricating oil outlet communicates with the lubricating oil inlet, wherein The upper part has a stepped part, and an outer culvert air inlet connected to the receiving chamber is arranged on the stepped part; a T-shaped spool is arranged in the receiving chamber, and the T-shaped spool can adjust the lubricating oil between the lubricating oil inlet and the lubricating oil outlet. Flow rate, the outer side of which is provided with a sealing groove, the sealing groove is provided with an expansion ring, and the T-shaped valve core is provided with a spring outer guide sleeve, wherein a sealing ring is provided between the end of the T-shaped valve core and the valve housing; The blocking cover fixedly connected with the valve housing is provided with a through hole communicating with the atmospheric environment, and the blocking cover is provided with a spring inner guide; the spring is arranged between the T-shaped valve core and the blocking cover. By constructing the steady-state control model of the oil valve in the low state and the steady-state control model in the high state, the opening and closing of the oil valve under the control of the trapped air is realized.

The invention provides a floating point processing unit integration circuit of an of RISC processor. The circuit comprises seven stages of fixed point pipelines, six stages of floating point pipelines and an and gate. An integration method includes the steps of controlling and managing processor pipeline stall and executing and controlling all the stages of the floating point pipelines. The floating point pipelines are correspondingly set, a storage access module access control logic and an exception handling module exception handling logic in the fixed point pipelines are used together, in this way, the floating point integration structure is made clear, less modification is conducted on the original fixed point pipeline design logic while the original fixed point processor logic is fully utilized, the control logic of the floating point pipes is reduced, and power consumption is lowered; the integration method has the universality, cooperative work of the fixed point pipelines and the floating point pipelines is achieved, fixed point command execution and floating point command execution are jointly achieved, reading of two source operands and writing-in of one operation result are completed within one clock period without other special waiting periods, and efficiency is high.

The invention relates to the communication technology and discloses an RS (reed Solomon) decoding method and device thereof in the communication system. By serial decomposition calculation of common parallel iBM algorithm, hardware resource required for solving key equations is greatly reduced and path delay is reduced under the condition of no influence on continuous decoding. Also, by combining and optimizing Chien search and Forney algorithm process, that is, odd-even terms in error position polynomial terminals and error value polynomial terms are split, and control logic and repeated calculation is reduced. Therefore, consumption of the hardware resource is only 1 / 2 to 1 / 3 of that of the common iBM algorithm, the maximum clock frequency and effective data bandwidth are improved by about 30%, high-speed channel error technology can be applied on a low-density chip, and cost is reduced.