Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Floating point processing unit integrated circuit and method of a risc processor

A processing unit and integrated circuit technology, applied in machine execution devices, concurrent instruction execution, etc., can solve problems such as many logic modifications, reduced instruction execution performance, and poor generality of integration methods, achieving wide selectivity and design logic changes. Small, floating point integrated structure for clear effect

Active Publication Date: 2017-05-31
NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
View PDF9 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The patent "Integrated System and Method of Extended Double-precision 80-bit Floating-point Processing Unit in Processor" (Application Publication No.: CN104156195A) provides a 5-stage double-precision extended double-precision 80-bit floating-point processing unit In the integrated method of the processor, but the integrated method needs to wait for the four-stage pipeline of the floating-point instruction to be executed before pre-decoding the fixed-point instruction, which directly reduces the execution performance of the instruction. In addition, a multi-precision floating-point The execution state of the instruction changes to the execution state of multiple single-cycle instructions. It is also necessary to control and manage the instruction fetch and pre-decoding module to ensure that no new instruction is read and decoded during the execution cycle of the floating-point instruction. The design logic of the processor pipeline has many modifications, and the integration method is not universal

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Floating point processing unit integrated circuit and method of a risc processor
  • Floating point processing unit integrated circuit and method of a risc processor
  • Floating point processing unit integrated circuit and method of a risc processor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0051] The present invention will be further described in detail below in conjunction with specific embodiments, which are explanations of the present invention rather than limitations.

[0052] The present invention aims at a processor with a seven-stage pipeline (instruction fetching stage, decoding stage, register access stage, execution stage, memory access stage, exception processing stage and data write-back stage), in order to make fixed-point instructions and floating-point instructions run efficiently.

[0053] First, if figure 1 As shown, on the basis of the seven-stage fixed-point pipeline, the instruction fetch stage, the decoding stage, the register access stage, the execution stage, the memory access stage, the exception handling stage, and the data write-back stage, the other six stages except the instruction fetch stage are added. The floating-point pipeline includes the decoding stage, register access stage, execution stage, memory access stage, exception hand...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a floating point processing unit integration circuit of an of RISC processor. The circuit comprises seven stages of fixed point pipelines, six stages of floating point pipelines and an and gate. An integration method includes the steps of controlling and managing processor pipeline stall and executing and controlling all the stages of the floating point pipelines. The floating point pipelines are correspondingly set, a storage access module access control logic and an exception handling module exception handling logic in the fixed point pipelines are used together, in this way, the floating point integration structure is made clear, less modification is conducted on the original fixed point pipeline design logic while the original fixed point processor logic is fully utilized, the control logic of the floating point pipes is reduced, and power consumption is lowered; the integration method has the universality, cooperative work of the fixed point pipelines and the floating point pipelines is achieved, fixed point command execution and floating point command execution are jointly achieved, reading of two source operands and writing-in of one operation result are completed within one clock period without other special waiting periods, and efficiency is high.

Description

technical field [0001] The invention relates to the field of embedded processors, in particular to a floating-point processing unit integrated circuit of a RISC processor and a method thereof. Background technique [0002] With the higher requirements for the computing precision of the processor in engineering applications, the processor is required to support single, double, and even quadruple-precision floating-point instruction operations, and the operations of floating-point instructions are mostly completed in independent floating-point execution units. For this reason, it should be studied how to integrate the floating-point processing unit according to the floating-point execution unit. [0003] At present, there are many technologies for improving the floating-point pipeline, such as the patent "full-expansion-based full-pipeline 128-bit precision floating-point accumulator" (CN 201010180381.8), "a five-stage pipeline structure of floating-point multiply-add fusion u...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38
Inventor 赵翠华张洵颖裴茹霞肖建青崔媛媛
Owner NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products