Method and device for transferring branch target prediction address in pipeline

A technology for predicting addresses and branch targets, applied in register devices, machine execution devices, instruments, etc., can solve problems such as complex pipeline design and large area overhead, and achieve the effects of reducing area overhead, small area overhead, and saving control logic

Active Publication Date: 2022-07-19
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

All of these lead to complex pipeline design and large area overhead

Method used

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  • Method and device for transferring branch target prediction address in pipeline
  • Method and device for transferring branch target prediction address in pipeline
  • Method and device for transferring branch target prediction address in pipeline

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Embodiment Construction

[0040] like figure 1 As shown, the method for transmitting the branch target prediction address in the pipeline in this embodiment includes:

[0041] 1) Initialize the read and write pointer of the predicted address queue and the number of free items in the queue register;

[0042] 2) In the instruction fetch stage, according to the branch direction prediction result, write the target predicted address of the branch predicted to jump into the predicted address queue, and update the queue write pointer and the queue free item number register;

[0043] 3) Pass the branch direction prediction result step by step with the pipeline;

[0044] 4) When dispatching the branch instruction of the predicted jump in the dispatch stage, use the read pointer to read the predicted address queue to obtain the target predicted address of the branch, and update the read pointer and the queue idle item number register;

[0045] 5) When the clearing operation of the pipeline occurs, reset the re...

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Abstract

The invention discloses a method and device for transmitting a branch target predicted address in a pipeline. The method includes initializing a read-write pointer of a predicted address queue and a queue free item number register; in the instruction fetch stage, according to the branch direction prediction result, the The target predicted address of the branch that predicts the jump is written into the predicted address queue, and the queue write pointer and the queue free item number register are updated; the branch direction prediction result is passed through the pipeline stage by stage; when the branch instruction of the predicted jump is dispatched in the dispatch stage, Use the read pointer to read the predicted address queue to obtain the target predicted address of the branch, and update the read pointer and the number of free items in the queue register; when the clearing operation of the pipeline occurs, reset the read and write pointer of the predicted address queue and the number of free items in the queue register. is the initial value. The present invention has the advantages of simple logic implementation and small area overhead.

Description

technical field [0001] The invention relates to the design technology of out-of-order multi-transmission microprocessors in the technical field of microprocessor design, in particular to a method and device for transmitting branch target prediction addresses in pipelines. Background technique [0002] When a microprocessor is designed, branch prediction technology is used to predict whether a branch instruction will jump and which address to jump to, that is, branch direction prediction and branch target prediction. Although the accuracy of branch prediction is getting higher and higher with the continuous development of branch prediction technology, branch prediction errors still exist. In order to judge whether the branch prediction is correct, it is necessary to pass the direction prediction result and target prediction result obtained in the branch prediction stage to the branch execution unit along with the pipeline. The direction prediction result has only one bit, 1 ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F9/30
CPCG06F9/3867G06F9/3806G06F9/30098
Inventor 孙彩霞邓全郭辉郭维雷国庆王俊辉郑重倪晓强黄立波隋兵才王永文
Owner NAT UNIV OF DEFENSE TECH
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