RS (Reed-Solomon) error correction decoder

An error-correcting code and decoder technology, applied in the field of error-correcting codes, can solve problems such as prolonging decoding time and calculating asynchronous

Active Publication Date: 2010-09-15
NEWLAND DIGITAL TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

When the existing RS error-correcting code decoder calculates the syndrome, the position calculation of the deletion position decoding error is performed in the previous step (or the next step) of the syndrome, although the de

Method used

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  • RS (Reed-Solomon) error correction decoder
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  • RS (Reed-Solomon) error correction decoder

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Embodiment Construction

[0055] Regarding the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings, which are provided for reference and illustration only, and are not intended to limit the present invention.

[0056] image 3 It is a circuit connection block diagram of the RS error correction code decoder of the present invention. like image 3 As shown, the RS error correction code decoder of the present invention includes a first-in-first-out buffer 601, an adder 602, a syndrome calculation circuit 603, a correction syndrome calculation circuit 604, a key equation solution circuit 605, an error value calculation circuit 606, and a deletion Position polynomial calculation circuit 607, money search circuit 608.

[0057] The workflow of the RS error-correcting code decoder of the present invention is as follows Figure 4 As shown, at first, in step 701, according to the received codeword r (x), the syndrome calculation...

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Abstract

The invention provides an RS (Reed-Solomon) error correction decoder which comprises an first-in first-out (FIFO) buffer, an adjoint computing circuit, a deleted location polynomial computing circuit, a correction adjoint computing circuit, a key equation solution circuit, a Chien search circuit, an error value computing circuit and a summator, wherein the deleted location polynomial computing circuit and the adjoint computing circuit are arranged in parallel. Through the arrangement, the RS error correction decoder can carry out adjoint computation and deleted location polynomial computationsynchronously, thereby increasing the decoding speed.

Description

【Technical field】 [0001] The invention belongs to the technical field of error correction codes, and in particular relates to an RS error correction code decoder. 【Background technique】 [0002] Error correction codes are widely used in information technology. Generally speaking, before the sending end sends information, the error correction encoder calculates the corresponding check code according to the data information to be sent, and uses the check code as a redundancy check and data information Together they form an error-correcting code. After the receiving end receives the error-correcting code, the error-correcting decoder can not only automatically find the error, but also automatically correct the error of the codeword during transmission. [0003] RS error correction code (Reed-Solomon error correction, Reed-Solomon error correction code) is a kind of cyclic code with strong error correction ability, usually the meaning of the symbol (N, K) RS is as follows: N rep...

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Application Information

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IPC IPC(8): H03M13/15
Inventor 胡伦育王贤福庄国梁陈朱管
Owner NEWLAND DIGITAL TECH CO LTD
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