Method for refreshing bulk-silicon floating body cell transistor memory

Abstract

The invention belongs to the technical field of dynamic random access memories, in particular to a method for refreshing a bulk-silicon floating body cell transistor memory, which comprises the step of: offsetting a voltage pulse on an implant layer of a bulk-silicon floating body cell (FBC) to ensure that a PN junction between the implant layer and a floating body cell region is weakly conductedso that the memory is changed from a strong 1 state into a weak 1 state or from a weak 0 state into a strong 0 state. The method has the characteristic of high refreshing reliability due to no utilization of a Charge Bumping effect. Meanwhile, for the FBC memory unit or memory, the read process does not exist in the refreshing process, thus a storage array of the FBC memory is integrally refreshed.

Description

Technical field [0001] The present invention belongs to the technical field of dynamic random access memory (DRAM), and particularly relates to a refresh operation method of a bulk silicon floating body transistor cell (Bulk Floating body transistor cell, Bulk FBC) memory. Background technique [0002] At present, as a replacement of 1T1C structured DRAM (Dynamic Random Access Memory) in the era of embedded memory, a new type of non-capacitor single-tube memory is being widely studied. This new type of memory is based on the principle of floating body effect (Floating Body Effect), so it is named Floating Body Transistor Cell (FBC). This kind of FBC memory only needs a single floating body transistor to complete the storage function, and the capacitor C is omitted, so the area is smaller. Moreover, compared with existing logic devices, no new materials are required, and the device structure is almost the same, and only two simple and easy processes need to be added to the conven...

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Problems solved by technology

Therefore, this causes a difference in the recombination situation. Some rows have no bound electrons on the surface due to no reading and writing during the refresh cycle, so the cells of these rows cannot achieve the recombination effect at all, that is, they cannot achieve " Weak 0" changes to "strong 0"; and some rows have accumulated too many bound electrons on the surface due to the frequent read and write times during the refresh cycle, which may cause a negative impact on the cells with a storage value of "1" during refresh. Aggravated, it is possible to pull the "strong 1" back to the "weak 1"

[0020] therefore, Figure 4 and Figure 5 The operation method of the FBC memory shown may have the problems of refresh misoperation and invalid refresh operation

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