Sensing device for floating body cell memory and method thereof

Abstract

A memory device includes a memory array and a sense amplifier. The memory array includes a floating body cell configured to store a bit value. The sense amplifier includes a bit output configured to provide an output voltage representative of the bit value and a reference source configured to provide a reference voltage. The sense amplifier further includes a current mirror configured to provide acurrent to the first floating body cell based on the reference voltage, and a differential amplifier circuit configured to determine the output voltage based on the reference voltage and a voltage across the floating body cell resulting from application of the current to the floating body cell.

Description

technical field [0001] The present invention relates generally to memory devices, and more particularly to sensing devices for floating body cell memory devices. Background technique [0002] Floating Body Cell (FBC) memory (also known as Zero-capacitor Random Access Memory (Z-RAMTM)) is achieved by Static Random Access Memory (SRAM) A compromise is provided between the speed of DRAM and the density achieved by Dynamic Random Access Memory (DRAM). FBCs typically use one or more transistors implemented on a Silicon On Insulator (SOI) substrate. By using the floating body effect generated by the transistor operating on the SOI substrate, the transistor can be configured like a capacitor to store charge, and then the amount of charge stored in the transistor can be read out to Determines the bit value stored by the transistor. [0003] Due to their physical characteristics, FBCs typically do not draw significant current. Therefore, the sense amplifier system used to read th...

AI Technical Summary

Problems solved by technology

However, conventional sense amplifiers for FBC memory typically have delayed response times and do not tolerate transistor mismatch within the sense circuit

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