Parallel turbo decoding with non-uniform window sizes

Abstract

A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbolsof the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded databetween the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder. Each of the upper and lower decoders include processing elements, which are configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper or lower convolutional encoder. The processing elements perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols. The configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively,during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to providethe a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder. The interleaving performed by the configurable network circuitry controlled by the network controller is in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle. Accordingly the processing elements can have a window size which includes a number of stages of the trellis so that the decoder can be configured with an arbitrary number of processing elements, making the decoder circuitan arbitrarily parallel turbo decoder.

Description

technical field [0001] The present disclosure relates to a detection circuit for performing a turbo detection process to recover from a received signal a frame of data symbols comprising one or more parities and / or a system for each data symbol of the frame Soft decision value. The data symbols of the frame have been encoded with a turbo encoder comprising an upper convolutional encoder and a lower convolutional encoder, each convolutional encoder can be represented by a trellis with multiple trellis states. [0002] Accordingly, embodiments of the present disclosure may provide a receiver configured to recover a frame of data symbols using a turbo decoder and a method for decoding turbo-encoded data. In one example, the data symbols are bits. [0003] This application claims Paris Convention priority to UK Patent Application 1702341.7, the contents of which are hereby incorporated by reference. Background technique [0004] Over the past two decades, wireless communicati...

AI Technical Summary

Problems solved by technology

In contrast, the processing throughput of state-of-the-art turbo decoders [10] is limited to 2.15Gbit / s

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