Delay reporting method and apparatus

Abstract

Provided in the embodiments of the present application is a delay reporting method. The method comprises: reporting target delays corresponding to data at a plurality of specific positions in a data stream, wherein the plurality of specific positions are spaced apart from each other by a fixed length, the period of the plurality of specific positions corresponds to the length of one or more convolutional interleaving sequences, and the specific positions correspond to delay lines having the maximum or minimum delay introduced in convolutional interleaving, alternatively, the period of the plurality of specific positions corresponds to the length of one or more distribution sequences, and each distribution sequence corresponds to eight distributed sub-sequences, alternatively, the period of the plurality of specific positions corresponds to an integer multiple of N data blocks, each of the N data blocks corresponds to one forward error correction (FEC) codeword, N is a positive integer, and the length of each data block is 120 bits, 128 bits, 110 bits or 126 bits. By using the present solution, a delay can be accurately reported.

Description

A delay reporting method and apparatus

[0001] This application claims priority to Chinese Patent Application No. 202410565639.8, filed on May 8, 2024, entitled "A Delay Reporting Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and more particularly to a delay reporting method and apparatus. Background Technology

[0003] Communication devices can exchange data. The sending end can send messages to the receiving end, adding a sending timestamp to the message. Similarly, after receiving a message, the receiving end can record its receiving timestamp for subsequent processing. For example, in a time synchronization scenario, the receiving end can perform time synchronization based on the sending and receiving timestamps. Here, the sending end can be understood as the communication device that sends the message, and the receiving end as the communication device that receives it.

[0004] The accuracy of the aforementioned sending and receiving timestamps directly affects the accuracy of the results obtained from subsequent processing measures. For example, in a time synchronization scenario, the accuracy of the sending and receiving timestamps directly affects the precision of time synchronization.

[0005] Therefore, how the sending end can accurately determine the sending timestamp of the message and how the receiving end can accurately determine the receiving timestamp of the message are problems that urgently need to be solved. Summary of the Invention

[0006] This application provides a latency reporting method and apparatus that can accurately report latency.

[0007] Firstly, this application provides a latency reporting method, which can be applied to a first module. The first module can report the target latency corresponding to data at multiple specific locations in a data stream, with a fixed interval between these multiple specific locations. In a specific example, the period of the multiple specific locations corresponds to the length of one or more convolutional interleaving sequences. When the first module corresponds to the transmitting end, the specific location corresponds to the delay line with the maximum latency introduced by the convolutional interleaving; when the first module corresponds to the receiving end, the specific location corresponds to the delay line with the minimum latency introduced by the convolutional interleaving. In this scenario, when the first module corresponds to the transmitting end, the target latency corresponding to the data at this specific location is equivalent to the maximum latency introduced by the convolutional interleaving operation; when the first module corresponds to the receiving end, the target latency corresponding to the data at this specific location is equivalent to the minimum latency introduced by the deconvolutional deinterleaving operation. In yet another specific example, the period of the multiple specific locations corresponds to the length of one or more distribution sequences, each of which corresponds to eight distributed sub-sequences. In this scenario, when the first module corresponds to the transmitting end, the target latency corresponding to the data at that specific location is equivalent to the maximum latency introduced by the distribution operation. When the first module corresponds to the receiving end, the target latency corresponding to the data at that specific location is equivalent to the minimum latency introduced by the multiplexing operation. In another specific example, the periods of the multiple specific locations correspond to integer multiples of N data blocks. Each of the N data blocks corresponds to a forward error correction (FEC) codeword, where N is a positive integer. The length of each data block is: 120 bits, or 128 bits, or 110 bits, or 126 bits. In this scenario, when the first module corresponds to the transmitting end, the target latency corresponding to the data at that specific location is equivalent to the maximum latency introduced by the internal code FEC encoding operation. When the first module corresponds to the receiving end, the target latency corresponding to the data at that specific location is equivalent to the minimum latency introduced by the FEC internal code decoding operation. Therefore, in this embodiment, if the first module corresponds to the transmitting end, the target latency corresponding to the data at that specific location is equivalent to the maximum latency; if the first module corresponds to the receiving end, the target latency corresponding to the data at that specific location is equivalent to the minimum latency. Thus, it can be seen that this solution can accurately report latency.

[0008] In one possible implementation, convolutional interleaving corresponds to three delay lines, and the delay line that introduces the maximum or minimum latency is the first delay line among the three delay lines in convolutional interleaving. Specifically, when the first module corresponds to the transmitting end, the delay line that introduces the maximum latency is the first delay line among the three delay lines in convolutional interleaving; when the first module corresponds to the receiving end, the delay line that introduces the minimum latency is the first delay line among the three delay lines in convolutional interleaving.

[0009] In one possible implementation, for the transmitting end, when performing the convolutional interleaving operation, the first delay line is used to delay each received data unit by 2*Q*D bits, the second delay line is used to delay each received data unit by Q*D bits, and the third delay line does not perform a delay operation on each received data unit. Here, D is the number of bits in each data unit, and Q is a positive integer. For the receiving end, when performing the deconvolutional deinterleaving operation, the third delay line is used to delay each received data unit by 2*Q*D bits, the second delay line is used to delay each received data unit by Q*D bits, and the first delay line does not perform a delay operation on each received data unit.

[0010] In one example, the value of Q is related to the interface rate. When the interface rate corresponds to 200G BASE-R, Q = 544. When the interface rate corresponds to 400G BASE-R, Q = 272. When the interface rate corresponds to 800G BASE-R, Q = 136. When the interface rate corresponds to 1.6T BASE-R, Q = 68.

[0011] In one possible implementation, convolutional interleaving corresponds to three delay lines, and the delay line that introduces the maximum or minimum latency is the third delay line among the three delay lines in convolutional interleaving. Specifically, when the first module corresponds to the transmitting end, the delay line that introduces the maximum latency is the third delay line among the three delay lines in convolutional interleaving; when the first module corresponds to the receiving end, the delay line that introduces the minimum latency is the third delay line among the three delay lines in convolutional interleaving.

[0012] In one possible implementation, for the transmitting end, when performing the convolutional interleaving operation, the first delay line does not perform a delay operation on each received data unit; the second delay line of the three delay lines delays each received data unit by 6*D bits; and the third delay line of the three delay lines delays each received data unit by 12*D bits, where D is the number of bits included in each data unit. For the receiving end, when performing the convolutional interleaving operation, the third delay line does not perform a delay operation on each received data unit; the second delay line delays each received data unit by 6*D bits; and the first delay line delays each received data unit by 12*D bits.

[0013] In one possible implementation, the number of data units included in each convolutional interleaving sequence is equal to the number of delay rows in the convolutional interleaving. For example, the number of delay rows could be 3 rows, in which case each convolutional interleaving sequence could include 3 data units. In one example, each of the 3 data units includes 40 bits. In other words, each convolutional interleaving sequence could include 120 bits.

[0014] In one possible implementation, the sending end can perform a 1:8 distribution operation on a distribution sequence, that is, distribute the distribution sequence into 8 streams. In this scenario, each distribution sequence can include 8 data blocks, and each stream can be distributed one data block. The data block distributed in each stream can also be referred to as a subsequence of the distribution sequence. In other words, after a distribution sequence is processed by a 1:8 distribution operation, 8 subsequences can be obtained. Correspondingly, the receiving end can perform an 8:1 multiplexing operation on the data blocks in the 8 streams to obtain the distribution sequence. In this scenario, since the waiting latency of the data block distributed in the first stream is the longest when the sending end performs the 1:8 distribution operation, and the waiting latency of the data block in the first stream is the shortest when the receiving end performs the 8:1 multiplexing operation, the specific position can correspond to the first stream among the aforementioned 8 streams.

[0015] In one possible implementation, if the sending end needs to perform 8:1 codeword interleaving after performing internal code FEC encoding, then the aforementioned value of N can be 8. In other words, the period of the multiple specific positions corresponds to an integer multiple of 8 data blocks, and each of the 8 data blocks corresponds to one FEC codeword.

[0016] In one possible implementation, if the sending end needs to perform 32:1 codeword interleaving after performing internal code FEC encoding, then the aforementioned value of N can be 32. In other words, the period of the multiple specific positions corresponds to an integer multiple of 32 data blocks, and each of the 32 data blocks corresponds to one FEC codeword.

[0017] In one possible implementation, the FEC codeword is an FEC internal codeword that has undergone external code FEC encoding and then internal code FEC encoding. In this scenario, the aforementioned data stream can be a data stream that has undergone external code FEC encoding and is received by the module performing internal code FEC through the attachment unit interface (AUI).

[0018] In one possible implementation, the FEC codeword is a Hamming codeword. In a specific example, the sending end can perform internal code FEC encoding using Hamming code encoding and perform 8:1 codeword interleaving on the resulting FEC codeword.

[0019] In one possible implementation, the FEC codeword is a BCH (Bose Chaudhuri Hocquenghem) codeword. In a specific example, the transmitter can use BCH code encoding to perform internal code FEC encoding and perform 32:1 codeword interleaving on the resulting FEC codeword.

[0020] In one possible implementation, after receiving the FEC codeword encoded with internal code, the receiving end can perform internal code FEC decoding on the FEC codeword. In one example, if the aforementioned first module corresponds to the receiving end, then the aforementioned data stream can also be the data stream obtained by the receiving end performing internal code FEC decoding.

[0021] In one possible implementation, considering that the starting position of the convolutional interleaving sequence introduces the greatest delay for the transmitting end when performing convolutional interleaving operations, and the starting position of the convolutional interleaving sequence introduces the least delay for the receiving end when performing deconvolutional deinterleaving operations, the specific position corresponds to the starting position of the one or more convolutional interleaving sequences. The starting position can be the first bit, the first symbol, or the first byte.

[0022] In one possible implementation, considering that the starting position of the distribution sequence introduces the greatest delay for the sending end during its distribution operation, and the starting position of the distribution sequence introduces the least delay for the receiving end during its multiplexing operation, the specific position corresponds to the starting position of the one or more distribution sequences.

[0023] In one possible implementation, considering that the starting positions of the aforementioned N data blocks introduce the greatest delay when the transmitter performs internal code FEC encoding, and the starting positions of the aforementioned N data blocks introduce the least delay when the receiver performs internal code FEC decoding, the specific position corresponds to a starting position that is an integer multiple of the N data blocks.

[0024] In one possible implementation, each of the aforementioned data locations at multiple specific locations can correspond to a first delay. Therefore, the data at these multiple specific locations can correspond to multiple first delays. Considering that Section 90 of the Institute of Electrical and Electronics Engineers (IEEE) 802.3cx defines corresponding maximum and minimum delay registers for each layer of the physical layer, to ensure compatibility with the current IEEE 802.3cx Section 90 mechanism for reporting physical layer delays, the maximum and / or minimum value among the multiple first delays can be reported. In other words, the aforementioned target delay can be the maximum and / or minimum value among the multiple first delays. In this case, the first module can also measure the first delay corresponding to the data at each of the multiple specific locations to obtain multiple first delays, so as to report the maximum and / or minimum value of the multiple first delays, thereby realizing the reporting of delay information.

[0025] In one possible implementation, the first module reports the target latency; specifically, this target latency can be reported to the second module. In one example, the second module could be the media access control (MAC) layer module of the communication device. In this way, the MAC layer module can compensate its own recorded timestamps based on the target latency, thereby making the compensated timestamps more accurate.

[0026] Secondly, this application provides a latency reporting device, the device comprising: a sending unit, configured to report target latency corresponding to data at multiple specific locations in a data stream, wherein the multiple specific locations are spaced at fixed intervals; wherein: the period of the multiple specific locations corresponds to the length of one or more convolutional interleaving sequences, the specific locations corresponding to the delay lines that introduce the maximum or minimum latency in the convolutional interleaving; or, the period of the multiple specific locations corresponds to the length of one or more distribution sequences, each of the distribution sequences corresponding to 8 distributed sub-sequences; or, the period of the multiple specific locations corresponds to an integer multiple of N data blocks, each of the N data blocks corresponding to a forward error correction (FEC) codeword, where N is a positive integer, and the length of each data block is: 120 bits, or 128 bits, or 110 bits, or 126 bits.

[0027] In one possible implementation, the delay line with the maximum or minimum introduced delay is the first of the three delay lines in the convolutional interleaving.

[0028] In one possible implementation, the first delay line is used to delay each received data unit by 2*Q*D bits, the second delay line of the three delay lines is used to delay each received data unit by Q*D bits, and the third delay line of the three delay lines does not perform a delay operation on each received data unit, where D is the number of bits included in each data unit and Q is a positive integer; or, the third delay line is used to delay each received data unit by 2*Q*D bits, the second delay line is used to delay each received data unit by Q*D bits, and the first delay line does not perform a delay operation on each received data unit.

[0029] In one possible implementation, Q can take the value of 544, 272, 136, or 68.

[0030] In one possible implementation, the delay line with the maximum or minimum introduced delay is the third delay line among the three delay lines in the convolutional interleaving.

[0031] In one possible implementation, the first delay line does not perform a delay operation on each received data unit, the second of the three delay lines is used to delay each received data unit by 6*D bits, and the third of the three delay lines is used to delay each received data unit by 12*D bits, where D is the number of bits included in each data unit; or, the third delay line does not perform a delay operation on each received data unit, the second delay line is used to delay each received data unit by 6*D bits, and the first delay line is used to delay each received data unit by 12*D bits.

[0032] In one possible implementation, each of the convolutional interleaving sequences comprises three data units, each of which comprises 40 bits.

[0033] In one possible implementation, each distribution sequence includes 8 data blocks, each distribution sequence is used to perform 1:8 distribution processing, or each distribution sequence is the first of 8 streams corresponding to the 1:8 distribution processing or 8:1 multiplexing processing at the specific position of the sequence obtained by performing 8:1 multiplexing processing.

[0034] In one possible implementation, the value of N is 8 or 32; or the FEC codeword is an FEC internal codeword that has undergone external code FEC encoding and then internal code FEC encoding; or the FEC internal codeword is a Hamming codeword or a BCH codeword; or the data stream is a data stream received through the Attached Unit Interface (AUI); or the data stream is a data stream obtained by performing internal code FEC decoding.

[0035] In one possible implementation, the specific position corresponds to the start position of the one or more convolutional interleaving sequences; or, the specific position corresponds to the start position of the one or more distribution sequences; or, the specific position corresponds to the start position of an integer multiple of the N data blocks; the start position is the first bit, the first symbol, or the first byte.

[0036] In one possible implementation, the apparatus further includes: a processing unit, configured to measure a first delay corresponding to the data at each of the plurality of specific locations, to obtain a plurality of first delays; wherein the target delay includes the maximum and / or minimum value among the plurality of first delays.

[0037] In one possible implementation, the sending unit is configured to: report the target latency corresponding to the data at the plurality of specific locations in the data stream to the Media Access Control (MAC) layer.

[0038] Thirdly, embodiments of this application provide a delay reporting device, including a circuit, the circuit being used to perform the method described in the first aspect above and any one of the first aspects above.

[0039] Fourthly, embodiments of this application provide a physical layer (PHY) chip, which is used to perform the methods described in the first aspect above and any one of the first aspects above.

[0040] Fifthly, embodiments of this application provide an optical module for performing the methods described in the first aspect above and any one of the first aspects above. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1a is a schematic diagram of a communication device provided in an embodiment of this application;

[0043] Figure 1b is a schematic diagram of another communication device provided in an embodiment of this application;

[0044] Figure 1c is a schematic diagram of another communication device provided in an embodiment of this application;

[0045] Figure 1d is a schematic diagram of the operations included in an internal code FEC provided in an embodiment of this application;

[0046] Figure 1e is a schematic diagram of a convolutional interleaving provided in an embodiment of this application;

[0047] Figure 1f is a schematic diagram of deconvolution deinterleaving provided in an embodiment of this application;

[0048] Figure 1g is a schematic diagram of the time delay introduced by convolutional interleaving and deconvolutional deinterleaving according to an embodiment of this application;

[0049] Figure 1h is a schematic diagram of a 120-bit block distribution provided in an embodiment of this application;

[0050] Figure 1i is a schematic diagram of the delay introduced by 120-bit block distribution and 120-bit block multiplexing according to an embodiment of this application;

[0051] Figure 1j is a schematic diagram of the delay introduced by the internal code FEC encoding or decoding function provided in an embodiment of this application;

[0052] Figure 1k is a schematic diagram of the operations included in an internal code FEC provided in an embodiment of this application;

[0053] Figure 1L is a schematic diagram of a convolutional interleaving provided in an embodiment of this application;

[0054] Figure 1m is a schematic diagram of the time delay introduced by convolutional interleaving and deconvolutional deinterleaving according to an embodiment of this application;

[0055] Figure 1n is a schematic diagram of the delay introduced by the internal code FEC encoding or decoding function provided in an embodiment of this application;

[0056] Figure 2 is a flowchart illustrating a delay reporting method provided in an embodiment of this application;

[0057] Figure 3 is a schematic diagram of the structure of a first module provided in an embodiment of this application;

[0058] Figure 4 is a schematic diagram of a delay reporting device provided in an embodiment of this application;

[0059] Figure 5 is a schematic diagram of the structure of a PHY chip or optical module provided in an embodiment of this application;

[0060] Figure 6 is a schematic diagram of the structure of a device provided in an embodiment of this application;

[0061] Figure 7 is a schematic diagram of the structure of a device provided in an embodiment of this application. Detailed Implementation

[0062] This application provides a latency reporting method and apparatus that can accurately report latency.

[0063] To make it easier to understand, we will first introduce the application scenarios of report latency.

[0064] In time synchronization scenarios, communication devices can synchronize their time by exchanging messages. The communication devices mentioned in this application embodiment can be network devices such as switches, routers, slice packet network (SPN) devices, or optical transmission network (OTN) devices. They can also be components of network devices, such as single boards, line cards, or interfaces, functional modules, chips, pluggable optical modules, servers, network cards on servers, or network cards of other devices. This application embodiment does not impose specific limitations. Communication devices can be directly connected, for example, via Ethernet cables or optical fibers.

[0065] The 1588 protocol is a high-precision time synchronization protocol. It provides time synchronization accuracy at the nanosecond (ns) level. Currently, the International Telecommunication Union (ITU-T) G.8273.2 defines four classes of time synchronization accuracy requirements: Class A, Class B, Class C, and Class D. Class A corresponds to a time accuracy of ±100 ns; Class B to ±70 ns; Class C to ±30 ns; and Class D to ±5 ns. Therefore, in one example, communication devices can synchronize their time by exchanging 1588 messages. The 1588 messages mentioned here can be understood as messages conforming to the 1588 protocol.

[0066] In the implementation of time synchronization between communication devices, the sending device can add a sending timestamp to the 1588 message, indicating the time of transmission. Similarly, the receiving device records the receiving timestamp, indicating the time of reception. Furthermore, the receiving device can perform time synchronization based on these sending and receiving timestamps. Since these timestamps are input parameters for time synchronization, their accuracy directly affects the precision of the synchronization. In other words, ensuring the accuracy of the sending and receiving timestamps is crucial.

[0067] Currently, communication devices record timestamps through their MAC layer. In a specific scenario, for communication devices that include an Ethernet interface, the MAC layer can record the timestamps.

[0068] Next, we will introduce how the communication device records timestamps, taking into account its structure.

[0069] Referring to Figure 1a, this figure is a schematic diagram of the structure of a communication device provided in an embodiment of this application, including the structure of the transmitting end communication device and the structure of the receiving end communication device.

[0070] As shown in Figure 1a, both the communication device acting as the transmitter and the communication device acting as the receiver can include a MAC layer and a physical layer. The physical layer can further include a physical coding sublayer (PCS), a physical medium attachment (PMA), and a physical media dependent layer (PMD). In addition, it can also include an application layer, which may correspond to upper-layer services, for example.

[0071] As the sending end, its MAC layer can generate MAC frames and send them to the physical layer. For example, the MAC layer can receive data sent by upstream devices or upper-layer services, and encapsulate the data to form MAC frames. Alternatively, if the MAC layer does not receive data from upstream devices or upper-layer services, it will generate a corresponding MAC frame based on the idle bitstream.

[0072] The MAC layer at the sending end transmits the MAC frame to the physical layer at the sending end. The physical layer may include PCS, PMA, and PMD. The MAC layer at the sending end can record the timestamp of its transmission of the MAC frame to the physical layer as the aforementioned transmission timestamp.

[0073] The PCS can process the received data stream and send the processed data to the PMA. The data stream mentioned here can be a bit stream consisting of multiple bits, which can be obtained by processing MAC frames.

[0074] PMA can modulate data from PCS into a signal that the channel supports for transmission.

[0075] PMD stands for signal transmitter, used to transmit PMA-modulated signals through a transmission medium.

[0076] The physical layer of the receiving end receives the signal transmitted through the aforementioned transmission medium, processes the signal, and then passes it to the MAC layer of the receiving end. As mentioned above, the physical layer of the receiving end also includes PMD, PMA, and PCS.

[0077] The receiving end's PMD first receives the signal transmitted on the transmission medium. Then, the PMA demodulates the signal. The data obtained after PMA demodulation is passed to the PCS, which performs corresponding operations on the received data. The operations performed by the receiving end's PCS are the inverse operations performed by the sending end's PCS. Further, the PCS can send the processed data stream to the MAC layer. Thus, after receiving the data stream sent by the PCS, the receiving end's MAC layer can obtain the MAC frame sent by the sending end and further process the MAC frame, for example, parsing the MAC frame and sending it to upstream devices or upper-layer services. When the receiving end's MAC layer receives the data stream processed by the PCS, it can record the timestamp of receiving the data stream as a reception timestamp.

[0078] To support the high-precision time synchronization feature of 1588, the physical layer of the communication device can report the latency of the data stream passing through the physical layer to the MAC layer. This allows the MAC layer to compensate for the latency when recording the transmission and reception timestamps of 1588 messages, making the timestamps more accurate after compensation. Specifically:

[0079] For the sending end, the MAC layer can add the aforementioned data stream's latency through the physical layer to its own recorded timestamp to obtain a transmission timestamp. It's easy to understand that this transmission timestamp can be considered the timestamp when the sending end's physical layer actually transmits the data stream.

[0080] For the receiving end, the MAC layer can subtract the latency of the data stream passing through the physical layer from its own recorded timestamp to obtain the received timestamp. It's easy to understand that this received timestamp can be considered the timestamp when the physical layer of the receiving end actually receives the data stream.

[0081] As described above, the data stream transmitted at the physical layer is a bitstream consisting of multiple bits. The physical layer cannot identify which parts of the bitstream correspond to 1588 packets. Therefore, the physical layer cannot accurately calculate the latency of 1588 packets. To solve this problem, in some scenarios, it is necessary to ensure the stability of the physical layer latency. That is, the latency of the data stream passing through the physical layer should stabilize around a fixed value. In this way, the physical layer can report this fixed value to the MAC layer, and the MAC layer can accordingly compensate for the timestamp based on this fixed value.

[0082] It should be noted that any communication device can act as both a transmitter and a receiver. In other words, the roles of the transmitter and receiver shown in Figure 1a can be interchanged. If the roles of the transmitter and receiver shown in Figure 1a are interchanged, the direction of the data flow will also change accordingly. That is, the direction of the data flow can be from the transmitter after the role interchange to the receiver after the role interchange.

[0083] In some scenarios, the PCS of the physical layer of a communication device may include FEC functionality. Referring to Figure 1b, which is a schematic diagram of another communication device provided in an embodiment of this application, the structure of the communication device shown in Figure 1b is basically the same as that shown in Figure 1a, except that the PCS of the communication device shown in Figure 1b includes FEC functionality.

[0084] For the communication device shown in Figure 1b, the FEC function at the transmitting end performs FEC encoding, which includes adding a parity bit. Additionally, the transmitting end performs data stream interleaving. Similarly, the PCS at the receiving end performs FEC decoding, which includes removing the parity bit. Furthermore, the receiving end performs deinterleaving on the data stream.

[0085] In one example, the FEC function of the PCS can also be called the external code FEC function. The FEC codeword obtained by the PCS at the sending end through FEC encoding can be called the FEC external codeword.

[0086] Furthermore, the current IEEE 802.3dj task force (B400G standard) defines physical layer support for concatenated coding. Specifically, an inner code FEC is inserted between the PMA and PMD for FEC encoding and decoding. As an example, the FEC codeword obtained by encoding the transmitter's inner code FEC using the inner code FEC can be referred to as the FEC inner code codeword.

[0087] Refer to Figure 1c for further understanding. Figure 1c is a schematic diagram of another communication device provided in an embodiment of this application. As shown in Figure 1c, the physical layer of the communication device supporting concatenated coding includes: a PCS supporting FEC function, PMA 101, PMA 102, internal code FEC, and PMD. PMA 101 and PMA 102 interact via AUI.

[0088] PCS and PMA 101 can belong to the first chip, while PMA102, internal code FEC, and PMD can belong to the optical module.

[0089] The internal code FEC performs operations related to the internal code.

[0090] In one example, the operations included in the internal code FEC can be understood with reference to Figure 1d, which is a schematic diagram of the operations included in an internal code FEC provided by an embodiment of this application.

[0091] As shown in Figure 1d:

[0092] For the transmitting end, the operations performed by the internal code FEC include: convolutional interweaving, 120-bit block distribution, internal code FEC processing, 8:1 four-level pulse amplitude modulation 4 (PAM4) interweaving, 1024-bit pad insertion, and other processing. Internal code FEC processing may include circular shifting and internal code FEC encoding, while other processing includes PAM4 encoding.

[0093] Correspondingly, for the receiving end, the operations performed by the inner code FEC include: other processing, inner code FEC synchronization and pad removal, 1:8 PAM4 deinterleaving, inner code FEC processing, 120-bit block multiplexing, and deconvolutional deinterweaving. Among these, inner code FEC processing may include cyclic shifting and inner code FEC decoding, while other processing includes PAM4 encoding.

[0094] in:

[0095] Convolutional interleaving involves various design parameters, including the number of delay lines, the delay block length, and the number of delay blocks. In one example, the number of delay lines in convolutional interleaving can be 3, corresponding to line 0, line 1, and line 2 in Figures 1e and 1f. The delay block length can correspond to D in Figures 1e and 1f; for example, D can be 40 bits. The number of delay blocks can correspond to Q in Figures 1e and 1f, and the number of delay blocks can be different for each delay line. Taking 3 delay lines as an example, the number of delay blocks can be 0, D, and 2D, respectively, resulting in 0 (no delay operation), 2*Q*D, and Q*D delay bits, respectively. Furthermore, when different numbers of delay blocks are selected, the number of delay bits for each delay line can also be 0 (no delay operation), 6*D, and 12*D, as shown in Figure 1L.

[0096] As a concrete example, the convolutional interleaving operation at the sending end sends 40 bits (each 40 bits is called a data unit) to three delay lines in a round-robin manner. Referring to Figure 1e, which is a schematic diagram of convolutional interleaving provided in an embodiment of this application, these three delay lines correspond to line 0, line 1, and line 2 in Figure 1e, respectively. Line 0 is also called the first delay line, line 1 is also called the second delay line, and line 2 is also called the third delay line. As shown in Figure 1e, line 0 (i.e., the first delay line) can delay each received data unit (corresponding to D in the leftmost and rightmost small squares in Figure 1e) by 2*Q*D bits; line 1 (i.e., the second delay line) can delay each received data unit by Q*D bits; and line 2 (i.e., the third delay line) does not perform a delay operation on each received data unit. Wherein:

[0097] In 2*Q*D and 2*Q*D, D represents the number of bits in each data unit; that is, the value of D in 2*Q*D and 2*Q*D is 40. Q is a positive integer. In one example, the value of Q is related to the interface rate of the communication device: Q = 544 when the interface rate corresponds to 200GBASE-R; Q = 272 when the interface rate corresponds to 400G BASE-R; Q = 136 when the interface rate corresponds to 800G BASE-R; and Q = 68 when the interface rate corresponds to 1.6T BASE-R.

[0098] Similarly, the deconvolution deinterleaving operation at the receiving end also sends every 40 bits to the three delay lines in a polling manner. The processing operations of the three delay lines at the receiving end are the opposite of those at the sending end, as shown in Figure 1f. Figure 1f is a schematic diagram of deconvolution deinterleaving provided by an embodiment of this application. As shown in Figure 1f, line 2 (i.e., the third delay line) can delay each received data unit by 2*Q*D bits, line 1 (i.e., the second delay line) can delay each received data unit by Q*D bits, and line 0 (i.e., the first delay line) does not perform a delay operation on each received data unit.

[0099] In one example, three data units sent sequentially to three delay lines can also be referred to as a convolutional interleaving sequence. In other words, when the number of delay lines is 3, a convolutional interleaving sequence can include 3 data units (i.e., 120 bits). When the number of delay lines is N, the number of data units included in the convolutional interleaving sequence is also N.

[0100] Because the three delay lines have different delays for data units during convolutional interleaving or deconvolutional deinterleaving operations, these operations introduce a sawtooth-shaped delay. This can be understood with reference to Figure 1g, which is a schematic diagram of the delay introduced by convolutional interleaving and deconvolutional deinterleaving according to an embodiment of this application. In Figure 1g, the horizontal axis represents the bitstream after convolutional interleaving or deconvolutional deinterleaving, and the vertical axis represents the delay. TX represents the delay introduced by the convolutional interleaving operation at the transmitting end, and RX represents the delay introduced by the deconvolutional deinterleaving operation at the receiving end.

[0101] In Figure 1g, the period of the sawtooth wave corresponds to the length of 3 data blocks, and the time corresponding to the length of 3 data blocks is:

[0102] 3*40 / (106.25G*2)≈0.5647ns.

[0103] The amplitude of the sawtooth wave is: 2*Q*40 / (106.25G*2). The amplitude of the sawtooth wave varies depending on the value of Q. Specifically:

[0104] If Q equals 544, then the amplitude of the sawtooth wave is: 2*544*40 / (106.25G*2)≈204.8ns;

[0105] If Q equals 272, then the amplitude of the sawtooth wave is: 2*272*40 / (106.25G*2)≈102.4ns;

[0106] If Q equals 136, then the amplitude of the sawtooth wave is: 2*136*40 / (106.25G*2)≈51.2ns;

[0107] If Q equals 68, then the amplitude of the sawtooth wave is: 2*68*40 / (106.25G*2)≈25.6ns.

[0108] In the above calculation formula: 106.25G*2 is the bit rate of the data stream for convolutional interleaving (or deconvolutional deinterleaving), and "2*Q*40" means that one symbol includes 2 bits, and 40 is the number of bits included in one data unit.

[0109] As described above regarding the convolutional interleaving performed at the transmitting end and the deconvolutional deinterleaving performed at the receiving end, for the transmitting end, the first delay line introduces the largest delay, and the delay corresponding to the data at the beginning of a convolutional interleaving sequence corresponds to the maximum delay introduced by the transmitting end performing the convolutional interleaving operation. For the receiving end, the first delay line introduces the smallest delay, and the delay corresponding to the data at the beginning of a convolutional interleaving sequence corresponds to the minimum delay introduced by the receiving end performing the deconvolutional deinterleaving operation. Specifically, the positions circled by the hollow and solid circles in Figure 1g correspond to the first delay line, and these positions also correspond to the beginning of a convolutional interleaving sequence.

[0110] In the embodiments of this application, the starting position includes, but is not limited to, the first bit, the first symbol, or the first byte.

[0111] In Figure 1g, the period of the empty circle and the period of the solid circle both correspond to 120 bits, which is the length of 3 data units, with each data unit being 40 bits long.

[0112] The 120-bit block distribution operation at the sending end distributes each 120-bit data block to eight Inner FEC flows according to a round-robin principle, and then sends them out uniformly. Refer to Figure 1h for understanding; Figure 1h is a schematic diagram of a 120-bit block distribution provided by an embodiment of this application. As shown in Figure 1h, these eight Inner FEC flows correspond to Inner FEC flow0 to Inner FEC flow7. Inner FEC flow0 can be considered the first flow among these eight Inner FEC flows, Inner FEC flow1 can be considered the second flow among these eight Inner FEC flows, and so on, with Inner FEC flow7 being considered the eighth flow among these eight Inner FEC flows. As shown in Figure 1h, 120-bit blocks 0 to 7 are sequentially distributed to Inner FEC flows 0 to 7, and 120-bit blocks 8 to 15 are sequentially distributed to Inner FEC flows 0 to 7. This 120-bit block distribution process results in the longest data latency for flow 0 and the shortest for flow 7. The 120-bit block multiplexing at the receiving end is the reverse process of 120-bit block distribution. The receiving end merges the data from the eight Inner FEC flows into one, resulting in the shortest data latency for flow 0 and the longest for flow 7.

[0113] Because the waiting times for data on each Inner FEC flow at the transmitting and receiving ends differ, the 120-bit block distribution and 120-bit block multiplexing operations introduce a sawtooth-shaped delay. This can be understood with reference to Figure 1i, which is a schematic diagram illustrating the delay introduced by 120-bit block distribution and 120-bit block multiplexing according to an embodiment of this application. In Figure 1i, the horizontal axis represents the bitstream after 120-bit block distribution or 120-bit block multiplexing processing, and the vertical axis represents the delay. TX represents the delay introduced by the 120-bit block distribution operation at the transmitting end, and RX represents the delay introduced by the 120-bit block multiplexing operation at the receiving end.

[0114] In Figure 1i, the period of the sawtooth wave corresponds to a length of 8 120 bits, and the time corresponding to the length of 8 120 bits is: 8*120 / (106.25G*2)≈4.5176ns.

[0115] The amplitude of the sawtooth wave is also approximately 4.5176 ns.

[0116] In one example, the eight 120-bit sequences sequentially distributed to eight inner FEC flows can also be referred to as a distribution sequence. In other words, a distribution sequence can include 8 * 120 = 960 bits. That is, the length of the distribution sequence corresponds to the product of the number of data streams after distribution and the length of the convolutional interleaving sequence. When the number of streams after distribution is N, the number of bits included in the distribution sequence is also N * 120 bits.

[0117] As described above regarding the 120-bit block distribution performed by the transmitting end and the 120-bit block multiplexing performed by the receiving end, for the transmitting end, the delay introduced by the starting position of a distribution sequence is the largest. In other words, the delay corresponding to the data at the starting position of a distribution sequence corresponds to the maximum delay introduced by the transmitting end in performing a 120-bit block distribution operation. For the receiving end, the delay introduced by the starting position of a distribution sequence is the smallest. In other words, the delay corresponding to the data at the starting position of a distribution sequence corresponds to the minimum delay introduced by the receiving end in performing a 120-bit block multiplexing operation. The starting position in the distribution sequence corresponds to Inner FEC flow 0. Specifically, the positions circled by the hollow and solid circles in Figure 1i correspond to the starting positions of the distribution sequence and also to Inner FEC flow 0.

[0118] In Figure 1i, the period of the empty circle and the period of the solid circle both correspond to 960 bits.

[0119] The transmitting end's internal code FEC encoding could, for example, insert 8 parity bits for every 120 message bits. Combined with the 8:1 codeword interleaving after internal code FEC encoding, this is equivalent to inserting 64 parity bits every 960 message bits. The receiving end performs the reverse process, removing 64 parity bits every 960 message bits. In this scenario, the FEC codeword obtained after internal code FEC encoding can be a Hamming codeword.

[0120] The addition or deletion of check bits during the internal code FEC encoding and decoding process introduces a sawtooth-shaped delay. Refer to Figure 1j for understanding; Figure 1j is a schematic diagram illustrating the delay introduced by the internal code FEC encoding or decoding function according to an embodiment of this application. Wherein:

[0121] The period of the sawtooth wave is approximately 4.5 ns (1024 / 113.4375G / 2), and the amplitude of the sawtooth wave is approximately 0.28125 ns (64 / 113.4375G / 2).

[0122] In formula 1024 / 113.4375G / 2:

[0123] 1024 corresponds to the number of bits contained in 8 FEC codewords, and one FEC codeword contains 128 bits;

[0124] 113.4375G corresponds to the baud rate of a single physical lane;

[0125] 2 indicates that in the scenario of PAM4 encoding of a data stream, a symbol consists of 2 bits;

[0126] In formula 64 / 113.4375G / 2:

[0127] 64 indicates that in 8:1 codeword interleaving, the first bit of the ninth virtual lane is the 65th bit in the interleaved data, and it needs to wait for the first 64 bits to be sent before it can be sent.

[0128] 113.4375G corresponds to the baud rate of a single physical channel;

[0129] 2 indicates that a symbol consists of 2 bits.

[0130] As described above for Figure 1j, the period of the sawtooth wave corresponds to 8 data blocks. Each data block corresponds to an FEC internal codeword, which is a Hamming codeword. For example, a data block may include 128 bits, which correspond to an FEC internal codeword encoded in Hamming code. Alternatively, a data block may include 120 bits, which, after Hamming code encoding, yields a 128-bit FEC internal codeword. In Figure 1i, the positions circled by the hollow and solid circles correspond to the starting positions of the aforementioned 8 data blocks. For the transmitting end, the delay corresponding to the position circled by the hollow circle represents the maximum delay introduced by the transmitting end performing the internal code FEC encoding operation. For the receiving end, the delay corresponding to the position circled by the solid circle represents the minimum delay introduced by the receiving end performing the internal code decoding operation.

[0131] In Figure 1g, the period of the free circle and the period of the solid circle both correspond to 8 data blocks. In one example, a data block consists of 128 bits, and in another example, a data block consists of 120 bits.

[0132] In this system, data blocks can be numbered sequentially, with an interval of m data blocks between two adjacent circles. This interval can be represented by the difference in numbers between the data blocks corresponding to the two adjacent circles. In this case, the period of the positions marked by the aforementioned circles is also m. For example, the interval between data blocks corresponding to two hollow circles can be 8 data blocks, which can be represented by the difference in numbers between the data blocks corresponding to the two hollow circles. Accordingly, the period of the positions marked by the hollow circles is 8.

[0133] In another example, the operations included in the internal code FEC can be understood with reference to Figure 1k, which is a schematic diagram of the operations included in an internal code FEC provided by an embodiment of this application. The operations included in the internal code FEC shown in Figure 1k are different from those included in the internal code FEC shown in Figure 1d. Generally, Figure 1d is applicable to short-range communication scenarios, while Figure 1k is applicable to long-range communication scenarios.

[0134] As shown in Figure 1k:

[0135] For the transmitting end, the operations performed by the internal code FEC include: alignment lock and lane deskew, lane reorder, permutation, convolutional interleaving, BCH encoding, cyclic shift, BCH interleaving, pilot insertion, dual polarization 16-state quadrature amplitude modulation (DP-16QAM) encoding, and digital-to-analog conversion via a digital-to-analog converter (DAC).

[0136] Correspondingly, for the receiving end, the operations performed by the internal code FEC include: via analog to digital converter (ADC), DP-16QAM decoding, BCH deinterleaving, pilot removal, cyclic shift, BCH decoding, deconvolution deinterleaving, and inverse permutation.

[0137] in:

[0138] The convolutional interleaving operation at the transmitting end sends 40 bits (each 40 bits is called a data unit) to three delay lines in a round-robin fashion, as shown in Figure 1L. Figure 1L is a schematic diagram of convolutional interleaving provided in an embodiment of this application. These three delay lines correspond to line 0, line 1, and line 2 in Figure 1L, respectively. Line 0 is also called the first delay line, line 1 is also called the second delay line, and line 2 is also called the third delay line. As shown in Figure 1L, line 0 (i.e., the first delay line) does not perform a delay operation on each received data unit, line 1 (i.e., the second delay line) can delay each received data unit by 6*D bits, and line 2 (i.e., the third delay line) can delay each received data unit by 12*D bits. Where D is the number of bits included in each data unit, i.e., D is 40.

[0139] Similarly, the deconvolution deinterleaving operation at the receiving end also sends every 40 bits to the three delay lines in a polling manner. The processing operations of the three delay lines at the receiving end are the opposite of those at the sending end. Line 2 (i.e., the first delay line) does not perform a delay operation on each data unit it receives. Line 1 (i.e., the second delay line) can delay each data unit it receives by 6*D bits. Line 0 (i.e., the third delay line) can delay each data unit it receives by 12*D bits.

[0140] In one example, three data units sent sequentially to three delay lines can also be referred to as a convolutional interleaving sequence. In other words, a convolutional interleaving sequence can include three data units (i.e., 120 bits).

[0141] Because the three delay lines have different delays for data units during convolutional interleaving or deconvolutional deinterleaving operations, these operations introduce a sawtooth-shaped delay. This can be understood by referring to Figure 1m, which is a schematic diagram of the delay introduced by convolutional interleaving and deconvolutional deinterleaving according to an embodiment of this application. In Figure 1m, the horizontal axis represents the bitstream after convolutional interleaving or deconvolutional deinterleaving, and the vertical axis represents the delay. TX represents the delay introduced by the convolutional interleaving operation at the transmitting end, and RX represents the delay introduced by the deconvolutional deinterleaving operation at the receiving end.

[0142] In Figure 1m, the period of the sawtooth wave corresponds to the length of 3 data blocks, and the time corresponding to the length of 3 data blocks is: 3*40 / (106.25G / 4)≈4.5176ns.

[0143] The amplitude of the sawtooth wave corresponds to the following time for 12*D bits: 12*40 / (106.25G / 4)≈18.0706ns. Where:

[0144] 106.25G / 4 is the bit rate at which the data stream is processed by convolutional interleaving (or deconvolutional deinterleaving).

[0145] As described above regarding the convolutional interleaving performed at the transmitting end and the deconvolutional deinterleaving performed at the receiving end, it can be seen that the third delay line introduces the greatest delay for the transmitting end, and the least delay for the receiving end. Specifically, the positions circled by the hollow and solid circles in Figure 1m correspond to the third delay line.

[0146] In Figure 1m, the period of both the empty circles and the period of the solid circles correspond to 120 bits.

[0147] The transmitting end's internal code FEC encoding could, for example, insert 16 parity bits for every 110 information bits. Combined with the 32:1 codeword interleaving after internal code FEC encoding, this is equivalent to inserting 512 parity bits every 3520 information bits. The receiving end performs the reverse process, removing 512 parity bits every 3520 information bits.

[0148] The addition or deletion of check bits during the internal code FEC encoding and decoding process introduces a sawtooth-shaped delay. Refer to Figure 1n for understanding; Figure 1n is a schematic diagram illustrating the delay introduced by the internal code FEC encoding or decoding function according to an embodiment of this application. Wherein:

[0149] The period of the sawtooth wave is approximately 126*32 / (106.25G / 4)≈151.7929ns, and the amplitude of the sawtooth wave is approximately 512 / (106.25G / 4)≈19.2753ns.

[0150] As described above for Figure 1n, the period of the sawtooth wave corresponds to 32 data blocks. Each data block corresponds to one FEC internal codeword, which is a BCH codeword. For example, a data block may include 126 bits, which correspond to one FEC internal codeword encoded by BCH. Alternatively, a data block may include 110 bits, which, after being encoded by BCH, yields a 126-bit FEC internal codeword. In Figure 1n, the positions circled by the hollow and solid circles correspond to the starting positions of the aforementioned 32 data blocks. For the transmitting end, the delay corresponding to the position circled by the hollow circle represents the maximum delay introduced by the transmitting end performing the internal code FEC encoding operation. For the receiving end, the delay corresponding to the position circled by the solid circle represents the minimum delay introduced by the receiving end performing the FEC internal code decoding operation.

[0151] In Figure 1n, the period of the empty circle and the period of the solid circle both correspond to 32 data blocks. In one example, a data block consists of 126 bits, and in another example, a data block consists of 110 bits.

[0152] Regarding the aforementioned delay introduced by the internal code FEC function, the Institute of Electrical and Electronics Engineers (IEEE) 802.3cx standard stipulates that: for the transmitting end, the reported delay is equivalent to the maximum delay, and for the receiving end, the reported delay is equivalent to the minimum delay.

[0153] However, the IEEE 802.3cx standard does not specify the specific implementation methods for the transmitter to report the maximum latency and the receiver to report the minimum latency in scenarios where the physical layer supports concatenated coding.

[0154] Furthermore, the existing IEEE 802.3cx Chapter 90 requires that when the physical layer of a communication device reports latency, each layer should report the maximum latency and minimum latency separately. Specifically, IEEE 802.3cx Chapter 90 defines the registers used by each layer to report the maximum and minimum latency. For example, IEEE 802.3cx Chapter 90 defines the TX maximum latency register, TX minimum latency register, RX maximum latency register, and RX minimum latency register for the PMA / PMD, where:

[0155] The PMA / PMD TX maximum delay register is used to report the maximum delay of the PMA / PMD when the communication device is acting as the transmitter.

[0156] The PMA / PMD's TX minimum delay register is used to report the minimum delay of the PMA / PMD when the communication device is acting as the transmitter.

[0157] The PMA / PMD's RX maximum delay register is used to report the maximum delay of the PMA / PMD when the communication device is acting as the receiver.

[0158] The RX minimum delay register of the PMA / PMD is used to report the minimum delay of the PMA / PMD when the communication device is acting as the receiver.

[0159] In view of this, embodiments of this application provide a latency reporting method. For multiple operations performed by the internal code FEC, the latency corresponding to each of the multiple operations can be determined separately, so as to report the latency corresponding to each operation to the MAC layer. The solution provided by embodiments of this application can accurately report latency in scenarios where the physical layer supports concatenated coding, while adhering to the EEE 802.3cx standard, which stipulates that "for the sender, the reported latency is equivalent to the maximum latency, and for the receiver, the reported latency is equivalent to the minimum latency."

[0160] Next, the delay reporting method provided in the embodiments of this application will be described in conjunction with the accompanying drawings.

[0161] Before introducing the latency reporting method provided in the embodiments of this application, it should be noted that:

[0162] For a communication device, it may include a physical layer module, which implements the functions of the aforementioned physical layer. The physical layer may include multiple sub-modules, each implementing a specific physical layer function. For example, the physical layer module may include a PCS sub-module, a PMA sub-module, and a PMD sub-module. The PCS sub-module implements the functions of the aforementioned PCS, the PMA sub-module implements the functions of the aforementioned PMA, and the PMD sub-module implements the functions of the aforementioned PMD.

[0163] In addition, the communication device may also include an optical module, which may further include corresponding sub-modules to implement corresponding functions. For example, for a communication device with the structure shown in Figure 1c, the optical module may include a PMA sub-module, an internal code FEC module, and a PMD sub-module. The internal code FEC module is used to implement the internal code FEC function.

[0164] Furthermore, time synchronization is only one application scenario provided by the embodiments of this application, and the solution of the embodiments of this application can also be applied to other scenarios. For example, in the scenario of flow detection, the communication device can also use the solution of the embodiments of this application to determine the sending timestamp or receiving timestamp of the message. The application scenarios of the embodiments of this application will not be listed and described one by one here.

[0165] Referring to Figure 2, this figure is a flowchart illustrating a delay reporting method provided in an embodiment of this application.

[0166] The delay reporting method shown in Figure 2 can be applied to a first module, which can be a module in a communication device. The communication device mentioned here can be a communication device acting as a transmitter or a communication device acting as a receiver; this application embodiment does not specifically limit this. The structure of the first module can be as shown in Figure 3, which is a schematic diagram of the structure of a first module provided in an embodiment of this application. As shown in Figure 3, the first module includes a bitstream processing module, a delay determination module, and a delay reporting module. The bitstream processing module can include an FEC module and other modules that interact with the FEC module. The delay determination module is used to determine the delay, and the delay reporting module is used to report the determined delay to the second module.

[0167] In one example, the first module can be a PHY module or an optical module. As a specific example, the structure of the communication device including the first module is as shown in Figure 1c. In this case, the FEC module shown in Figure 3 can be a module that implements the internal code FEC function, and the module that implements the internal code FEC function can also be called an "internal code FEC module".

[0168] The PHY module mentioned in the embodiments of this application may be, for example, a PHY chip used to implement PHY functions.

[0169] The method described in Figure 2 may include the following steps S101-S102.

[0170] S101: Determine the target latency corresponding to data at multiple specific locations in the data stream, wherein the multiple specific locations are spaced at fixed intervals, and the period of the multiple specific locations corresponds to the length of one or more convolutional interleaving sequences, wherein the specific locations correspond to the delay lines that introduce the maximum or minimum latency in the convolutional interleaving; or, the period of the multiple specific locations corresponds to the length of one or more distribution sequences, wherein each distribution sequence corresponds to 8 distributed sub-sequences; or, the period of the multiple specific locations corresponds to an integer multiple of N data blocks, wherein each of the N data blocks corresponds to a forward error correction (FEC) codeword, where N is a positive integer, and the length of each data block is: 120 bits, or 128 bits, or 110 bits, or 126 bits.

[0171] In this embodiment of the application, the data stream is a bit stream comprising multiple bits.

[0172] In one example, the first module can be the module corresponding to the internal code FEC shown in Figure 1d. If the first module is the module corresponding to the transmitting end, then the first module can perform convolutional interleaving, 120-bit block distribution, and internal code FEC encoding operations on the data entering the first module. Correspondingly, if the first module is the module corresponding to the receiving end, then the first module can perform FEC internal code decoding, 120-bit block multiplexing, and deconvolutional deinterleaving operations on the data entering the first module. In this case:

[0173] In one example, the target latency can be the latency introduced by the transmitting end performing convolutional interleaving. In this case, the periods at the multiple specific positions correspond to the lengths of one or more convolutional interleaving sequences. As described earlier, a convolutional interleaving sequence can include three 40-bit sequences, i.e., a convolutional interleaving sequence includes 120 bits. In this case, referring to the previous description of Figure 1g, the latency corresponding to the positions circled by the hollow circles in Figure 1g is the maximum latency corresponding to the transmitting end performing the convolutional interleaving operation. Therefore, the periods at the multiple specific positions correspond to the periods of the hollow circles in Figure 1g; for example, the periods at these multiple specific positions can be integer multiples of the periods of the hollow circles in Figure 1g. In other words, the periods at the multiple specific positions can correspond to the lengths of one or more convolutional interleaving sequences. In this scenario, the positions circled by the hollow circles in Figure 1g correspond to the delay line with the maximum introduced latency, and the delay line with the minimum introduced latency is the first of the three delay lines. For the transmitting end, its first delay line can delay each received data unit by 2*Q*D bits, its second delay line can delay each received data unit by Q*D bits, and its third delay line does not perform any delay operation on each received data unit. The values ​​of data unit, Q, and D can be found in the previous description of Figure 1g, and will not be repeated here.

[0174] In this scenario, the data stream can be either the data stream entering the convolutional interleaving module at the transmitting end or the data stream processed by the convolutional interleaving module, which performs convolutional interleaving processing. Before entering the convolutional interleaving module, the data stream may undergo external code FEC encoding processing via the PCS at the transmitting end. Referring to Figure 1c, this data stream undergoing external code FEC encoding processing can be passed to PMA101 of the PCS and then to PMA102 of the optical module via AUI. Further, PMA102 of the optical module passes it to the internal code FEC, so that the convolutional interleaving module of the internal code FEC can further perform convolutional interleaving processing.

[0175] As described above regarding the position circled by the hollow circle in Figure 1g, the position circled by the hollow circle can correspond to the starting position of the convolutional interleaving sequence. In other words, the specific position corresponds to the starting position of one or more convolutional interleaving sequences.

[0176] In another example, the target latency can be the latency introduced by the receiving end performing deconvolution deinterleaving. In this case, the periods at the multiple specific positions correspond to the lengths of one or more convolutional interleaving sequences. As described earlier, a convolutional interleaving sequence can include three 40-bit sequences, i.e., a convolutional interleaving sequence includes 120 bits. In this case, referring to the previous description of Figure 1g, the latency corresponding to the positions circled by the solid circles in Figure 1g is the minimum latency corresponding to the receiving end performing deconvolution deinterleaving. Therefore, the periods at the multiple specific positions can correspond to the periods of the solid circles in Figure 1g; for example, the periods at these multiple specific positions can be integer multiples of the periods of the solid circles in Figure 1g. In other words, the periods at the multiple specific positions can correspond to the lengths of one or more convolutional interleaving sequences. In this scenario, the positions circled by the solid circles in Figure 1g correspond to the delay line with the minimum introduced latency, which is the first of the three delay lines. In this design, the first delay line at the receiving end does not perform a delay operation on each received data unit. The second delay line at the receiving end can delay each received data unit by Q*D bits. The third delay line at the receiving end can delay each received data unit by 2*Q*D bits. The values ​​of Q and D can be found in the previous description of Figure 1g, and will not be repeated here.

[0177] In this scenario, as an example, the data stream can be a data stream sent from the sending end to the receiving end, and this data stream can be a data stream entering the convolutional interleaving module of the receiving end. As another example, the data stream can also be a data stream processed by the convolutional interleaving module of the receiving end, wherein the convolutional interleaving module of the receiving end is used to perform deconvolutional deinterleaving processing.

[0178] As described above regarding the position circled by the solid circle in Figure 1g, the position circled by the solid circle can correspond to the starting position of the convolutional interleaving sequence. In other words, the specific position corresponds to the starting position of one or more convolutional interleaving sequences.

[0179] In the embodiments of this application, the first module is a module corresponding to the sending end, which can be understood as the first module being a module in the communication device that acts as the sending end; the first module is a module corresponding to the receiving end, which can be understood as the first module being a module in the communication device that acts as the receiving end. Wherein, the first module corresponding to the receiving end can also be understood as the first module corresponding to the receiving end, and the first module corresponding to the sending end can also be understood as the first module corresponding to the sending end.

[0180] In one example, the target latency can be the latency introduced by the sender performing a 120-bit block distribution. In this case, the periods at the multiple specific positions correspond to the lengths of one or more distribution sequences. The sender can perform a 1:8 distribution process on the distribution sequence, distributing multiple data blocks, each containing 120 bits, to eight inner FEC flows. As described above, a distribution sequence can include eight 120-bit blocks, i.e., a distribution sequence includes 960 bits. In this case, referring to the previous description of Figure 1i, the latency corresponding to the positions circled by the hollow circles in Figure 1i is the maximum latency corresponding to the sender performing a 120-bit block distribution operation. Therefore, the periods at the multiple specific positions correspond to the periods of the hollow circles in Figure 1i; for example, the periods at these multiple specific positions can be integer multiples of the periods of the hollow circles in Figure 1i. In other words, the periods at the multiple specific positions can correspond to the lengths of one or more distribution sequences. In this scenario, the position circled in Figure 1i corresponds to the starting position of the distribution sequence and the first flow (i.e., the first inner FEC flow) corresponding to the 1:8 distribution processing.

[0181] In another example, the target latency can be the latency introduced by the receiver performing 120-bit block multiplexing. In this case, the periods at the multiple specific positions correspond to the lengths of one or more distribution sequences. The receiver can perform 8:1 multiplexing on the distribution sequence, combining 120-bit data blocks from eight inner FEC flows into a single data stream. Referring to the previous description of Figure 1i, the latency corresponding to the positions circled by the solid circles in Figure 1i is the minimum latency corresponding to the receiver performing 120-bit block multiplexing. Therefore, the periods at the multiple specific positions correspond to the periods of the solid circles in Figure 1i; for example, the periods at these multiple specific positions can be integer multiples of the periods of the solid circles in Figure 1i. In other words, the periods at the multiple specific positions can correspond to the lengths of one or more distribution sequences. In this scenario, the positions circled by the solid circles in Figure 1i correspond to the starting position of the distribution sequence and the first stream (i.e., the first inner FEC flow) corresponding to the 8:1 multiplexing process.

[0182] In one example, the target latency can be the latency introduced by the sending end performing internal code FEC encoding. In this case, the period of the multiple specific positions corresponds to an integer multiple of N data blocks. Referring to the previous description of Figure 1j, the latency corresponding to the position circled by the hollow circle in Figure 1j is the maximum latency corresponding to the sending end performing internal code FEC encoding. Therefore, the period of the multiple specific positions corresponds to the period of the hollow circle in Figure 1j; for example, the period of the multiple specific positions can be an integer multiple of the period of the hollow circle in Figure 1j. As described in the previous description of Figure 1j, the period of the hollow circle is 8 data blocks; therefore, in one example, the aforementioned N equals 8. In other words, the period of the multiple specific positions can correspond to an integer multiple of 8 data blocks. In this scenario, the position circled by the hollow circle in Figure 1j corresponds to the starting position of the aforementioned integer multiple of 8 data blocks. Each of the eight data blocks may include 128 bits or 120 bits, where the 128 bits are the FEC codeword obtained after Hamming code encoding, and the 120 bits are the data before Hamming code encoding.

[0183] In this scenario, as an example, the data stream can be a data stream entering the internal code FEC encoding module at the transmitting end, where the internal code FEC encoding module is used to perform internal code FEC encoding. Before entering the internal code FEC encoding module, the data stream may have undergone external code FEC encoding processing via the PCS at the transmitting end. Referring to Figure 1c, this data stream undergoing external code FEC encoding processing can be passed to PMA101 of the PCS and then to PMA102 of the optical module via AUI. Further, PMA102 of the optical module passes it to the internal code FEC, so that the convolutional interleaving module of the internal code FEC can further perform convolutional interleaving processing. As another example, the data stream can also be a data stream processed by the internal code FEC encoding module; in other words, the data stream can include FEC internal code codewords that have undergone external code FEC encoding processing and then internal code FEC encoding.

[0184] In another example, the target latency can be the latency introduced by the receiver performing internal code FEC decoding. In this case, the period of the multiple specific positions corresponds to an integer multiple of N data blocks. Referring to the previous description of Figure 1j, the latency corresponding to the position circled by the solid circle in Figure 1j is the minimum latency corresponding to the receiver performing internal code FEC decoding. Therefore, the period of the multiple specific positions corresponds to the period of the solid circle in Figure 1j; for example, the period of the multiple specific positions can be an integer multiple of the period of the solid circle in Figure 1j. As described in the previous description of Figure 1j, the period of the solid circle is 8 data blocks; therefore, in one example, N equals 8. In other words, the period of the multiple specific positions can correspond to an integer multiple of 8 data blocks. In this scenario, the position circled by the solid circle in Figure 1j corresponds to the starting position of the aforementioned integer multiple of 8 data blocks. Each of the eight data blocks may include 128 bits or 120 bits, where the 128 bits are the FEC codeword obtained after Hamming code encoding, and the 120 bits are the data before Hamming code encoding.

[0185] In this scenario, as an example, the data stream can be a data stream entering the internal code FEC decoding module at the receiving end, wherein the internal code FEC decoding module is used to perform internal code FEC decoding. As yet another example, the data stream can also be a data stream obtained by performing internal code FEC decoding via the internal code FEC decoding module.

[0186] In another example, the first module can be the module corresponding to the internal code FEC shown in Figure 1k. If the first module is the module corresponding to the transmitting end, then the first module can perform convolutional interleaving and internal code FEC encoding operations on the data entering the first module. Correspondingly, if the first module is the module corresponding to the receiving end, then the first module can perform FEC internal code decoding and deconvolutional deinterleaving operations on the data entering the first module. For this case:

[0187] In one example, the target latency can be the latency introduced by the transmitting end performing convolutional interleaving. In this case, the periods at the multiple specific positions correspond to the lengths of one or more convolutional interleaving sequences. As described earlier, a convolutional interleaving sequence can include three 40-bit sequences, i.e., a convolutional interleaving sequence includes 120 bits. In this case, referring to the previous description of Figure 1m, the latency corresponding to the positions circled by the hollow circles in Figure 1m is the maximum latency corresponding to the transmitting end performing the convolutional interleaving operation. Therefore, the periods at the multiple specific positions correspond to the periods of the hollow circles in Figure 1m; for example, the periods at these multiple specific positions can be integer multiples of the periods of the hollow circles in Figure 1m. In other words, the periods at the multiple specific positions can correspond to the lengths of one or more convolutional interleaving sequences. In this scenario, the positions circled by the hollow circles in Figure 1m correspond to the delay line with the maximum introduced latency, which is the third delay line out of the three delay lines. For the transmitting end, the first delay line does not need to perform a delay operation on each received data unit. The second delay line of the three delay lines can delay each received data unit by 6*D bits, and the third delay line of the three delay lines can delay each received data unit by 12*D bits. The value of D can be found in the previous description of Figure 1m, and will not be repeated here.

[0188] In this scenario, the data stream can be either the data stream entering the convolutional interleaving module at the transmitting end or the data stream processed by the convolutional interleaving module, which performs convolutional interleaving processing. Before entering the convolutional interleaving module, the data stream may undergo external code FEC encoding processing via the PCS at the transmitting end. Referring to Figure 1c, this data stream undergoing external code FEC encoding processing can be passed to PMA101 of the PCS and then to PMA102 of the optical module via AUI. Further, PMA102 of the optical module passes it to the internal code FEC, so that the convolutional interleaving module of the internal code FEC can further perform convolutional interleaving processing.

[0189] In another example, the target latency can be the latency introduced by the receiving end performing deconvolution deinterleaving. In this case, the periods at the multiple specific positions correspond to the lengths of one or more convolutional interleaving sequences. As described earlier, a convolutional interleaving sequence can include three 40-bit sequences, i.e., a convolutional interleaving sequence includes 120 bits. In this case, referring to the previous description of Figure 1m, the latency corresponding to the positions circled by the solid circles in Figure 1m is the minimum latency corresponding to the receiving end performing deconvolution deinterleaving. Therefore, the periods at the multiple specific positions can correspond to the periods of the solid circles in Figure 1m; for example, the periods at these multiple specific positions can be integer multiples of the periods of the solid circles in Figure 1m. In other words, the periods at the multiple specific positions can correspond to the lengths of one or more convolutional interleaving sequences. In this scenario, the positions circled by the solid circles in Figure 1m correspond to the delay line with the minimum introduced latency, which is the third delay line out of the three delay lines. In this configuration, the third delay line at the receiving end does not perform a delay operation on each received data unit. The second delay line at the receiving end can delay each received data unit by 6*D bits. The first delay line at the receiving end can delay each received data unit by 12*D bits. The value of D can be found in the previous description of Figure 1m, and will not be repeated here.

[0190] In this scenario, as an example, the data stream can be a data stream sent from the sending end to the receiving end, and this data stream can be a data stream entering the convolutional interleaving module of the receiving end. As another example, the data stream can also be a data stream processed by the convolutional interleaving module of the receiving end, wherein the convolutional interleaving module of the receiving end is used to perform deconvolutional deinterleaving processing.

[0191] In one example, the target latency can be the latency introduced by the transmitter performing internal code FEC encoding. In this case, the period of the multiple specific positions corresponds to an integer multiple of N data blocks. Referring to the previous description of Figure 1n, the latency corresponding to the position circled by the hollow circle in Figure 1n is the maximum latency corresponding to the transmitter performing internal code FEC encoding. Therefore, the period of the multiple specific positions corresponds to the period of the hollow circle in Figure 1n; for example, the period of the multiple specific positions can be an integer multiple of the period of the hollow circle in Figure 1n. As described in the previous description of Figure 1n, the period of the hollow circle is 32 data blocks; therefore, in one example, N equals 32. In other words, the period of the multiple specific positions can correspond to an integer multiple of 32 data blocks. In this scenario, the position circled by the hollow circle in Figure 1n corresponds to the starting position of the aforementioned integer multiple of 32 data blocks. Each of the 32 data blocks can include either 126 bits or 110 bits. The 126 bits are the FEC codeword obtained after BCH encoding, and the 110 bits are the data before BCH encoding.

[0192] In this scenario, as an example, the data stream can be a data stream entering the internal code FEC encoding module at the transmitting end, where the internal code FEC encoding module is used to perform internal code FEC encoding. Before entering the internal code FEC encoding module, the data stream may have undergone external code FEC encoding processing via the PCS at the transmitting end. Referring to Figure 1c, this data stream undergoing external code FEC encoding processing can be passed to PMA101 of the PCS and then to PMA102 of the optical module via AUI. Further, PMA102 of the optical module passes it to the internal code FEC, so that the convolutional interleaving module of the internal code FEC can further perform convolutional interleaving processing. As another example, the data stream can also be a data stream processed by the internal code FEC encoding module; in other words, the data stream can include FEC internal code codewords that have undergone external code FEC encoding processing and then internal code FEC encoding.

[0193] In another example, the target latency can be the latency introduced by the receiver performing internal code FEC decoding. In this case, the period of the multiple specific positions corresponds to an integer multiple of N data blocks. Referring to the previous description of Figure 1n, the latency corresponding to the position circled by the solid circle in Figure 1n is the minimum latency corresponding to the receiver performing internal code FEC decoding. Therefore, the period of the multiple specific positions corresponds to the period of the solid circle in Figure 1n; for example, the period of the multiple specific positions can be an integer multiple of the period of the solid circle in Figure 1n. As described in the previous description of Figure 1n, the period of the solid circle is 32 data blocks; therefore, in one example, N equals 32. In other words, the period of the multiple specific positions can correspond to an integer multiple of 32 data blocks. In this scenario, the position circled by the solid circle in Figure 1n corresponds to the starting position of the aforementioned integer multiple of 32 data blocks. Each of the 32 data blocks can include either 126 bits or 110 bits. The 126 bits are the FEC codeword obtained after BCH encoding, and the 110 bits are the data before BCH encoding.

[0194] In this scenario, as an example, the data stream can be a data stream entering the internal code FEC decoding module at the receiving end, wherein the internal code FEC decoding module is used to perform internal code FEC decoding. As yet another example, the data stream can also be a data stream obtained by performing internal code FEC decoding via the internal code FEC decoding module.

[0195] In one example, the data from the aforementioned multiple specific locations can correspond to a first time delay for each specific location. Therefore, the data from the aforementioned multiple specific locations can correspond to multiple first time delays.

[0196] In the embodiments of this application, the plurality of first delays may be the same, or may not be completely the same or completely different, and the embodiments of this application do not make specific limitations.

[0197] As mentioned earlier, the existing IEEE 802.3cx Chapter 90 defines corresponding maximum and minimum delay registers for each layer of the physical layer. Therefore, to be compatible with the current IEEE 802.3cx Chapter 90 mechanism for reporting physical layer delays, the maximum and / or minimum value among the plurality of first delays can be reported. In other words, the aforementioned target delay can be the maximum and / or minimum value among the plurality of first delays.

[0198] As mentioned above, the plurality of first delays may be the same, not exactly the same, or completely different. When the plurality of first delays are the same, the maximum value and the minimum value are the same. When the plurality of first delays are not exactly the same or completely different, the maximum value is less than the minimum value.

[0199] In one example, in a specific implementation of S101, the first module can measure the first delay corresponding to the data at each of the multiple specific locations, thus obtaining multiple first delays. For example:

[0200] The embodiments in this application do not specifically limit the specific implementation method of determining the first delay.

[0201] In one example, the first module can record the delay of data at a specific location in the data stream to determine the first delay. In another example, the first module can determine the delay of data at multiple locations in the data stream after passing through the first module, thereby obtaining multiple delays corresponding to the multiple locations. The multiple locations mentioned here may include the specific location; for example, the multiple locations may be various locations in the target data. Accordingly, the first delay can be determined from these multiple delays. That is, the delay corresponding to the specific location is extracted from the multiple delays to obtain the first delay. For example, for a data stream, the first module can determine the delay of each bit of data in the data stream after passing through the first module, and extract the delay of data at a specific location in the data stream (e.g., the start position of each convolutional interleaving sequence) after passing through the first module to obtain the first delay.

[0202] The method for determining the time delay of data at any position in the data stream after passing through the first module is not specifically limited in the embodiments of this application. Two possible implementation methods are described below.

[0203] In one implementation, the first module can record the first moment when it receives the data at that location, and the second moment when it sends the data at that location out. The difference between the second moment and the first moment is determined as the time delay of the data at that location passing through the first module.

[0204] In another example, after receiving data at a specific location, the first module can cache that data. Accordingly, the first module can send out the cached data in sequence, based on the already cached data. Therefore, the position of the data at that location in the cache can characterize the length of time the data at that location needs to wait in the cache, and this waiting time can characterize the latency of the data at that location passing through the first module. Thus, the first module can determine the latency of the data at that location passing through the first module based on the position of the data at that location in the cache.

[0205] S102: Report the target latency corresponding to data at multiple specific locations in the data stream.

[0206] In this embodiment, the first module can report the target latency to the second module. In one example, the second module can be the MAC layer module of a communication device. In this way, the MAC layer module can compensate for its own recorded timestamps based on the target latency, thereby making the compensated timestamps more accurate.

[0207] In one example, the first module can report the target latency separately to the second module, or it can add the target latency and the latency of other operations in the internal code FEC of the data stream and report them together to the second module. This application embodiment does not make specific limitations.

[0208] The first module can use corresponding registers to report the target latency to the second module. In a scenario where the target latency includes the aforementioned maximum and / or minimum values, in one example, the first module can use corresponding registers to report the maximum and / or minimum values ​​to the second module. The following describes several specific implementation methods of the first module using corresponding registers to report the maximum and / or minimum values ​​to the second module.

[0209] In one example, if the first module corresponds to the sending end, then:

[0210] As a concrete example, new registers can be defined to report the maximum and / or minimum values ​​to the second module. For instance, a maximum TX delay register and / or a minimum TX delay register can be defined for the internal code FEC, where the maximum TX delay register is used to report the maximum value and the minimum TX delay register is used to report the minimum value. In other words, the first module can use the maximum TX delay register of the internal code FEC to report the maximum value to the second module, and / or use the minimum TX delay register of the internal code FEC to report the minimum value to the second module.

[0211] As another concrete example, the first module can use the PMA / PMD's TX maximum delay register to report the maximum value to the second module. Similarly, the first module can use the PMA / PMD's TX minimum delay register to report the minimum value to the second module. In this way, existing registers can be used to report the target delay.

[0212] In one example, if the first module corresponds to the receiving end, then:

[0213] As another concrete example, new registers can be defined to report the maximum and / or minimum values ​​to the second module. For example, a maximum RX delay register and / or a minimum RX delay register can be defined for the internal code FEC, where the maximum RX delay register is used to report the maximum value and the minimum RX delay register is used to report the minimum value. In other words, the first module can use the maximum RX delay register of the internal code FEC to report the maximum value to the second module, and / or use the minimum RX delay register of the internal code FEC to report the minimum value to the second module.

[0214] As another specific example, the first module can use the RX maximum delay register of the PMA / PMD to report the maximum value to the second module. Similarly, the first module can use the RX minimum delay register of the PMA / PMD to report the minimum value to the second module.

[0215] As can be seen from the above description, using the scheme of this application embodiment, for the dynamically periodic delay portion (i.e., the delay portion in the shape of a sawtooth wave), the first module can accurately report the delay to the second module according to the principle that "for the sending end, the reported delay is equivalent to the maximum delay, and for the receiving end, the reported delay is equivalent to the minimum delay".

[0216] The latency reporting method provided by the embodiments of this application has been described above. Next, the solution provided by the embodiments of this application will be described in conjunction with specific scenarios.

[0217] In this scenario, the structure of the communication device can be as shown in Figure 1d. The first module can be the optical module of the communication device, which includes PMA102, internal code FEC and PMD.

[0218] Example 1:

[0219] For a communication device acting as a transmitter, its optical module can perform the following operations:

[0220] S1: Record the delay of the i-th convolutional interleaving sequence in the data stream it sends after the convolutional interleaving operation, and obtain DelayTX1(1, i), where:

[0221] 1 indicates the starting position, which can be the first bit, the first byte, or the first symbol.

[0222] The value of i can be 1, 2, 3, ..., s.

[0223] S2: Determine the maximum value of DelayTX1(1,i) DelayTX_max1 and the minimum value of DelayTX1(1,i) DelayTX_min1.

[0224] S3: Report DelayTX_max1 and DelayTX_min1 to the MAC layer module, or report (DelayTX_max1+sum11) and (DelayTX_min1+sum12) to the MAC layer module.

[0225] In one example, the TX maximum delay register of the internal code FEC can be used to report DelayTX_max1 or (DelayTX_max1+sum11) to the MAC layer module, and the TX minimum delay register of the internal code FEC can be used to report DelayTX_min1 or (DelayTX_min1+sum12) to the MAC layer module.

[0226] In another example, the TX maximum delay register of the PMA / PMD can be used to report DelayTX_max1 or (DelayTX_max1+sum11) to the MAC layer module, and the TX minimum delay register of the PMA / PMD can be used to report DelayTX_min1 or (DelayTX_min1+sum12) to the MAC layer module.

[0227] Here, sum11 can be the maximum sum of delays of the data stream through other operations, and sum12 can be the minimum sum of delays of the data stream through other operations. sum11 and sum12 can be the same, and sum11 can also be greater than sum12. Other operations mentioned here can be, for example, the 120-bit block distribution operation in internal code FEC, the internal code FEC encoding operation, etc.

[0228] For a communication device acting as a receiver, its optical module can perform the following operations:

[0229] S1': Records the delay of the i-th convolutional interleaved sequence in the data stream it sends after the convolutional interleaving operation, resulting in DelayRX1(1, i), where:

[0230] 1 indicates the starting position, which can be the first bit, the first byte, or the first symbol.

[0231] The value of i can be 1, 2, 3, ..., s.

[0232] S2': Determine the maximum value of DelayRX1(1,i) DelayRX_max1 and the minimum value of DelayRX1(1,i) DelayRX_min1.

[0233] S3': Report DelayRX_max1 and DelayRX_min1 to the MAC layer module, or report (DelayRX_max1+sum11') and (DelayRX_min1+sum12') to the MAC layer module.

[0234] In one example, the RX maximum delay register of the internal code FEC can be used to report DelayRX_max1 or (DelayRX_max1+sum11') to the MAC layer module, and the RX minimum delay register of the internal code FEC can be used to report DelayRX_min1 or (DelayRX_min1+sum12') to the MAC layer module.

[0235] In another example, the RX maximum delay register of the PMA / PMD can be used to report DelayRX_max1 or (DelayRX_max1+sum11') to the MAC layer module, and the RX minimum delay register of the PMA / PMD can be used to report DelayRX_min1 or (DelayRX_min1+sum12') to the MAC layer module.

[0236] Wherein, sum11' can be the maximum sum of delays of the data stream through other operations, and sum12' can be the minimum sum of delays of the data stream through other operations. sum11' and sum12' can be the same, and sum11' can also be greater than sum12'. Other operations mentioned here can be, for example, the 120-bit block multiplexing operation in the internal code FEC, the FEC internal code decoding operation, etc.

[0237] Example 2:

[0238] For a communication device acting as a transmitter, its optical module can perform the following operations:

[0239] S4: Record the delay of the i-th distributed sequence in the data stream after a 120-bit block distribution operation, and obtain DelayTX2(1,j), where:

[0240] 1 indicates the starting position, which can be the first bit, the first byte, or the first symbol.

[0241] The value of i can be 1, 2, 3, ..., s.

[0242] S5: Determine the maximum value of DelayTX2(1,j) DelayTX_max2 and the minimum value of DelayTX2(1,j) DelayTX_min2.

[0243] S6: Report DelayTX_max2 and DelayTX_min2 to the MAC layer module, or report (DelayTX_max2+sum21) and (DelayTX_min2+sum22) to the MAC layer module.

[0244] In one example, the TX maximum delay register of the internal code FEC can be used to report DelayTX_max2 or (DelayTX_max2+sum21) to the MAC layer module, and the TX minimum delay register of the internal code FEC can be used to report DelayTX_min2 or (DelayTX_min2+sum22) to the MAC layer module.

[0245] In another example, the maximum TX delay register of the PMA / PMD can be used to report DelayTX_max2 or (DelayTX_max2+sum21) to the MAC layer module, and the minimum TX delay register of the PMA / PMD can be used to report DelayTX_min2 or (DelayTX_min2+sum22) to the MAC layer module.

[0246] Here, sum21 can be the maximum sum of the delays of the data stream through other operations, and sum22 can be the minimum sum of the delays of the data stream through other operations. sum21 and sum22 can be the same, and sum21 can also be greater than sum22. The other operations mentioned here can be, for example, the convolution interleaving operation in internal code FEC, the internal code FEC encoding operation, etc.

[0247] For a communication device acting as a receiver, its optical module can perform the following operations:

[0248] S4': Records the delay of the i-th distributed sequence in the data stream after 120-bit block multiplexing, resulting in DelayRX2(1, j), where:

[0249] 1 indicates the starting position, which can be the first bit, the first byte, or the first symbol.

[0250] The value of i can be 1, 2, 3, ..., s.

[0251] S5': Determine the maximum value of DelayRX2(1,j) DelayRX_max2 and the minimum value of DelayRX2(1,j) DelayRX_min2.

[0252] S6': Report DelayRX_max2 and DelayRX_min2 to the MAC layer module, or report (DelayRX_max2+sum21') and (DelayRX_min2+sum22') to the MAC layer module.

[0253] In one example, DelayRX_max2 or (DelayRX_max2+sum21') can be reported to the MAC layer module through the RX maximum delay register of the internal code FEC, and DelayRX_min2 or (DelayRX_min2+sum22') can be reported to the MAC layer module through the RX minimum delay register of the internal code FEC.

[0254] In another example, DelayRX_max2 or (DelayRX_max2+sum21') can be reported to the MAC layer module through the RX maximum delay register of the PMA / PMD, and DelayRX_min2 or (DelayRX_min2+sum22') can be reported to the MAC layer module through the RX minimum delay register of the PMA / PMD.

[0255] Here, sum21' can be the maximum sum of the delays of the data stream through other operations, and sum22' can be the minimum sum of the delays of the data stream through other operations. sum21' can be equal to sum22', or sum21' can be greater than sum22'. The other operations mentioned here can be, for example, the deconvolution deinterleaving operation and the FEC code decoding operation in the internal code FEC.

[0256] Example 3:

[0257] For a communication device acting as a transmitter, its optical module can perform the following operations:

[0258] S7: Record the start position of the k-th data block in the transmitted data stream and the delay encoded by the internal code FEC, to obtain DelayTX3(1, k), where:

[0259] 1 indicates the starting position, which can be the first bit, the first byte, or the first symbol.

[0260] The value of k can be 8, 16, 32, ... 8*s, in which case a data block includes 128 bits or 120 bits; or, the value of k can be 32, 64, 96, ... 32*s, in which case a data block includes 126 bits or 110 bits.

[0261] S8: Determine the maximum value of DelayTX3(1,k) DelayTX_max3 and the minimum value of DelayTX3(1,k) DelayTX_min3.

[0262] S9: Report DelayTX_max3 and DelayTX_min3 to the MAC layer module, or report (DelayTX_max3+sum31) and (DelayTX_min3+sum32) to the MAC layer module.

[0263] In one example, the maximum TX delay register of the internal code FEC can be used to report DelayTX_max3 or (DelayTX_max3+sum31) to the MAC layer module, and the minimum TX delay register of the internal code FEC can be used to report DelayTX_min3 or (DelayTX_min3+sum32) to the MAC layer module.

[0264] In another example, the maximum TX delay register of the PMA / PMD can be used to report DelayTX_max3 or (DelayTX_max3+sum31) to the MAC layer module, and the minimum TX delay register of the PMA / PMD can be used to report DelayTX_min3 or (DelayTX_min3+sum32) to the MAC layer module.

[0265] Here, sum31 can be the maximum sum of the delays of the data stream through other operations, and sum32 can be the minimum sum of the delays of the data stream through other operations. sum31 can be equal to sum32, or sum31 can be greater than sum32. The other operations mentioned here can be, for example, the convolution interleaving operation in the internal code FEC, or the convolution interleaving operation and the 120-bit block distribution operation.

[0266] For a communication device acting as a receiver, its optical module can perform the following operations:

[0267] S7': Records the delay of the starting position of the k-th data block in the transmitted data stream via internal code FEC encoding, resulting in DelayRX3(1, k), where:

[0268] 1 indicates the starting position, which can be the first bit, the first byte, or the first symbol.

[0269] The value of k can be 8, 16, 32, ... 8*s, in which case a data block includes 128 bits or 120 bits; or, the value of k can be 32, 64, 96, ... 32*s, in which case a data block includes 126 bits or 110 bits.

[0270] S8': Determine the maximum value of DelayRX3(1,k) DelayRX_max3 and the minimum value of DelayRX(1,k) DelayRX_min3.

[0271] S9': Report DelayRX_max3 and DelayRX_min3 to the MAC layer module, or report (DelayRX_max3+sum31') and (DelayRX_min3+sum32') to the MAC layer module.

[0272] In one example, the maximum delay of DelayRX_max3 or (DelayRX_max3+sum31') can be reported to the MAC layer module through the RX maximum delay register of the internal code FEC, and the minimum delay of DelayRX_min3 or (DelayRX_min3+sum32') can be reported to the MAC layer module through the RX minimum delay register of the internal code FEC.

[0273] In another example, DelayRX_max3 or (DelayRX_max3+sum31') can be reported to the MAC layer module through the RX maximum delay register of the PMA / PMD, and DelayRX_min3 or (DelayRX_min3+sum32') can be reported to the MAC layer module through the RX minimum delay register of the PMA / PMD.

[0274] Here, sum31' can be the maximum sum of the delays of the data stream through other operations, and sum32' can be the minimum sum of the delays of the data stream through other operations. sum31' can be equal to sum32', or sum31' can be greater than sum32'. The other operations mentioned here can be, for example, the deconvolution deinterleaving operation in the internal code FEC, or the deconvolution deinterleaving operation and the 120-bit block multiplexing operation.

[0275] Based on the latency reporting method provided in the above embodiments, this application also provides a corresponding latency reporting device, which can be used to execute the latency reporting method provided in the above embodiments.

[0276] In a specific example, the delay reporting device can be as shown in Figure 4. Figure 4 is a schematic diagram of the structure of a delay reporting device provided in an embodiment of this application.

[0277] As shown in Figure 4, the delay reporting device 400 includes a sending unit 401.

[0278] The sending unit 401 is used to report the target latency corresponding to data at multiple specific locations in the data stream, wherein the multiple specific locations are spaced at fixed intervals; wherein: the period of the multiple specific locations corresponds to the length of one or more convolutional interleaving sequences, and the specific locations correspond to the delay lines with the maximum or minimum latency introduced in the convolutional interleaving; or, the period of the multiple specific locations corresponds to the length of one or more distribution sequences, and each distribution sequence corresponds to 8 distributed sub-sequences; or, the period of the multiple specific locations corresponds to an integer multiple of N data blocks, and each of the N data blocks corresponds to a forward error correction (FEC) codeword, where N is a positive integer, and the length of each data block is: 120 bits, or 128 bits, or 110 bits, or 126 bits.

[0279] In one possible implementation, the delay line with the maximum or minimum introduced delay is the first of the three delay lines in the convolutional interleaving.

[0280] In one possible implementation, the first delay line is used to delay each received data unit by 2*Q*D bits, the second delay line of the three delay lines is used to delay each received data unit by Q*D bits, and the third delay line of the three delay lines does not perform a delay operation on each received data unit, where D is the number of bits included in each data unit and Q is a positive integer; or, the third delay line is used to delay each received data unit by 2*Q*D bits, the second delay line is used to delay each received data unit by Q*D bits, and the first delay line does not perform a delay operation on each received data unit.

[0281] In one possible implementation, Q can take the value of 544, 272, 136, or 68.

[0282] In one possible implementation, the delay line with the maximum or minimum introduced delay is the third delay line among the three delay lines in the convolutional interleaving.

[0283] In one possible implementation, the first delay line does not perform a delay operation on each received data unit, the second of the three delay lines is used to delay each received data unit by 6*D bits, and the third of the three delay lines is used to delay each received data unit by 12*D bits, where D is the number of bits included in each data unit; or, the third delay line does not perform a delay operation on each received data unit, the second delay line is used to delay each received data unit by 6*D bits, and the first delay line is used to delay each received data unit by 12*D bits.

[0284] In one possible implementation, each of the convolutional interleaving sequences comprises three data units, each of which comprises 40 bits.

[0285] In one possible implementation, each distribution sequence includes 8 data blocks, each distribution sequence is used to perform 1:8 distribution processing, or each distribution sequence is the first of 8 streams corresponding to the 1:8 distribution processing or 8:1 multiplexing processing at the specific position of the sequence obtained by performing 8:1 multiplexing processing.

[0286] In one possible implementation, the value of N is 8 or 32; or the FEC codeword is an FEC internal codeword that has undergone external code FEC encoding and then internal code FEC encoding; or the FEC internal codeword is a Hamming codeword or a BCH codeword; or the data stream is a data stream received through the Attached Unit Interface (AUI); or the data stream is a data stream obtained by performing internal code FEC decoding.

[0287] In one possible implementation, the specific position corresponds to the start position of the one or more convolutional interleaving sequences; or, the specific position corresponds to the start position of the one or more distribution sequences; or, the specific position corresponds to the start position of an integer multiple of the N data blocks; the start position is the first bit, the first symbol, or the first byte.

[0288] In one possible implementation, the device 400 further includes: a processing unit 402, configured to measure a first delay corresponding to the data at each of the plurality of specific locations, and obtain a plurality of first delays; wherein the target delay includes the maximum and / or minimum value among the plurality of first delays.

[0289] In one possible implementation, the sending unit 401 is configured to: report the target latency corresponding to the data at the plurality of specific locations in the data stream to the Media Access Control (MAC) layer.

[0290] For the specific implementation of each unit of the device 400, please refer to the description of the delay reporting method provided in this application in the above embodiments. The device 400 can implement the delay reporting method described in the above embodiments, and will not be described again here. Each unit in the device 400 can be a software unit implemented by a computer program or a hardware unit implemented by a circuit.

[0291] In yet another specific example, the aforementioned delay reporting device may include circuitry for performing the delay reporting method provided in the above embodiments.

[0292] The delay reporting device mentioned in the embodiments of this application can be an optical module or a PHY chip.

[0293] In one example, the structure of the PHY chip or optical module can be as shown in Figure 5. Referring to Figure 5, this figure is a schematic diagram of the structure of a PHY chip or optical module provided in an embodiment of this application. The PHY chip or optical module 500 shown in Figure 5 includes an interface circuit 501 and a processing circuit 502. The interface circuit 501 is used to receive and / or transmit data, and the processing circuit 502 is used to perform data processing. The PHY chip or optical module 500 can implement the latency reporting method described in the above embodiments. The interface circuit 501 and the processing circuit 502 can be a division in terms of actual circuit structure, that is, the PHY chip or optical module 500 includes two parts of circuit, namely the interface circuit 501 and the processing circuit 502. Alternatively, the interface circuit 501 and the processing circuit 502 can be a division in terms of functional logic, that is, the PHY chip or optical module 500 includes an integrated circuit, which can implement the process of receiving and / or transmitting data corresponding to the interface circuit 501, and can also implement the process of data processing corresponding to the processing circuit 502.

[0294] In one example, the interface circuit 501 is used to report the target latency corresponding to data at multiple specific locations in the data stream, with a fixed interval between the multiple specific locations; wherein: the period of the multiple specific locations corresponds to the length of one or more convolutional interleaving sequences, and the specific location corresponds to the delay line with the maximum or minimum latency introduced in the convolutional interleaving; or, the period of the multiple specific locations corresponds to the length of one or more distribution sequences, each of the distribution sequences corresponding to 8 distributed sub-sequences; or, the period of the multiple specific locations corresponds to an integer multiple of N data blocks, each of the N data blocks corresponding to a forward error correction (FEC) codeword, where N is a positive integer, and the length of each data block is: 120 bits, or 128 bits, or 110 bits, or 126 bits. The processing circuit 502 is used to measure the first latency corresponding to the data at each specific location in the multiple specific locations, obtaining multiple first latencys; wherein, the target latency includes the maximum and / or minimum value among the multiple first latencys.

[0295] Referring to Figure 6, this figure is a schematic diagram of the structure of a device provided in an embodiment of this application. The device 600 shown in Figure 6 includes an interface circuit 601 and a processing circuit 602. The interface circuit 601 is used to receive and / or send data, and the processing circuit 602 is used to perform data processing. The device 600 can implement the delay reporting method described in the above embodiments. The interface circuit 601 and the processing circuit 602 can be divided in terms of actual circuit structure, that is, the device 600 includes two parts of circuit, namely the interface circuit 601 and the processing circuit 602. Alternatively, the interface circuit 601 and the processing circuit 602 can be divided in terms of functional logic, that is, the device 600 includes a single integrated circuit, which can implement the process of receiving and / or sending data corresponding to the interface circuit 601, and can also implement the data processing process corresponding to the processing circuit 602.

[0296] As a specific example, the interface circuit 601 is used to report the target latency corresponding to data at multiple specific locations in the data stream, with a fixed interval between the multiple specific locations; wherein: the period of the multiple specific locations corresponds to the length of one or more convolutional interleaving sequences, and the specific location corresponds to the delay line with the maximum or minimum latency introduced in the convolutional interleaving; or, the period of the multiple specific locations corresponds to the length of one or more distribution sequences, each of the distribution sequences corresponding to 8 distributed sub-sequences; or, the period of the multiple specific locations corresponds to an integer multiple of N data blocks, each of the N data blocks corresponding to a forward error correction (FEC) codeword, where N is a positive integer, and the length of each data block is: 120 bits, or 128 bits, or 110 bits, or 126 bits. The processing circuit 602 is used to measure the first latency corresponding to the data at each specific location in the multiple specific locations, obtaining multiple first latencys; wherein, the target latency includes the maximum and / or minimum value among the multiple first latencys.

[0297] Referring to Figure 7, this figure is a schematic diagram of the structure of a device provided in an embodiment of this application.

[0298] In one example, the device 700 shown in FIG7 can be used to execute the delay reporting method corresponding to FIG2 provided in the above method embodiments.

[0299] Please refer to Figure 7. The device 700 includes a communication interface 720. This communication interface 720 is used to execute the delay reporting method corresponding to Figure 2 provided in the above method embodiments.

[0300] In one example, the device 700 may further include a processor 710. The number of processors 710 in the device 700 can be one or more; Figure 7 shows an example of one processor. The processor 710 and the communication interface 720 jointly execute the latency reporting method corresponding to Figure 2 provided in the above method embodiments. For example, the processor 710 is used to measure a first latency corresponding to the data at each specific location in a data stream, obtaining a plurality of first latencys; wherein, the target latency includes the maximum and / or minimum value among the plurality of first latencys. The communication interface 720 is used to report the target latency corresponding to the data at multiple specific locations in the data stream.

[0301] Processor 710 may be a central processing unit (CPU), an NP, or a combination of CPU and NP. Processor 710 may include a digital signal processor (DSP). Processor 710 may further include hardware chips. The aforementioned hardware chips may be ASICs, programmable logic devices (PLDs), or combinations thereof. The aforementioned PLDs may be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof.

[0302] In one example, the device 700 further includes a memory 730. The memory 730 may include volatile memory, such as random-access memory (RAM); the memory 730 may also include non-volatile memory, such as flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); the memory 730 may also include combinations of the above types of memory. The memory 730 may, for example, store the aforementioned target delay.

[0303] Optionally, the memory 730 stores an operating system and programs, executable modules, or data structures, or subsets thereof, or extended sets thereof. The programs may include various operation instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and handling hardware-based tasks. The processor 710 can read the programs from the memory 730 to implement the methods provided in the embodiments of this application.

[0304] In this embodiment of the application, the processor 710, the communication interface 720 and the memory 730 can be connected through a bus system or other means, wherein FIG7 shows an example of being connected through a bus system 740.

[0305] The bus system 740 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus system 740 can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used in Figure 7, but this does not indicate that there is only one bus or one type of bus.

[0306] The latency reporting device 400, PHY chip or optical module 500, device 600 and device 700 provided above can all be network devices such as switches, routers, SPN devices or OTN devices, or they can be components of network devices, such as single boards, line cards or interfaces on network devices, or functional modules on network devices, or chips, or pluggable optical modules on network devices, or servers, network cards on servers, or network cards of other devices, etc. The embodiments of this application do not make specific limitations.

[0307] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0308] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0309] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical business division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0310] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0311] Furthermore, the various business units in the embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software business unit.

[0312] If the integrated unit is implemented as a software business unit and sold or used as a separate product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0313] Those skilled in the art will recognize that, in one or more of the examples above, the services described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these services can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of computer programs from one place to another. Storage media can be any available medium accessible to general-purpose or special-purpose computers.

[0314] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention.

[0315] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A delay reporting method, characterized in that, The method includes: The report defines the target latency corresponding to data at multiple specific locations in the data stream, with a fixed interval between these multiple specific locations; wherein: The period at the multiple specific positions corresponds to the length of one or more convolutional interleaving sequences, and the specific positions correspond to the delay lines with the maximum or minimum delay introduced in the convolutional interleaving; or, The period at the multiple specific positions corresponds to the length of one or more distribution sequences, and each distribution sequence corresponds to 8 distributed subsequences; or, The period of the multiple specific positions corresponds to an integer multiple of N data blocks, and each of the N data blocks corresponds to a forward error correction (FEC) codeword, where N is a positive integer. The length of each data block is: 120 bits, or 128 bits, or 110 bits, or 126 bits.

2. The method according to claim 1, characterized in that, The delay line with the maximum or minimum introduced delay is the first of the three delay lines in the convolutional interleaving.

3. The method according to claim 2, characterized in that, The first delay line is used to delay each received data unit by 2*Q*D bits, the second delay line of the three delay lines is used to delay each received data unit by Q*D bits, and the third delay line of the three delay lines does not perform a delay operation on each received data unit, where D is the number of bits included in each data unit and Q is a positive integer; or, The third delay line is used to delay each received data unit by 2*Q*D bits, the second delay line is used to delay each received data unit by Q*D bits, and the first delay line does not perform a delay operation on each received data unit.

4. The method according to claim 3, characterized in that, The value of Q can be 544, 272, 136, or 68.

5. The method according to claim 1, characterized in that, The delay line with the maximum or minimum introduced delay is the third delay line among the three delay lines in the convolutional interleaving.

6. The method according to claim 5, characterized in that, The first delay line does not perform a delay operation on each data unit it receives. The second delay line of the three delay lines is used to delay each data unit it receives by 6*D bits. The third delay line of the three delay lines is used to delay each data unit it receives by 12*D bits, where D is the number of bits included in each data unit. or, The third delay line does not perform a delay operation on each data unit it receives, the second delay line is used to delay each data unit it receives by 6*D bits, and the first delay line is used to delay each data unit it receives by 12*D bits.

7. The method according to any one of claims 1-6, characterized in that, Each of the convolutional interleaving sequences comprises three data units, each of which comprises 40 bits.

8. The method according to claim 1, characterized in that, Each of the distribution sequences includes 8 data blocks, and each of the distribution sequences is used to perform 1:8 distribution processing, or each of the distribution sequences is the first of 8 streams corresponding to the 1:8 distribution processing or 8:1 multiplexing processing at the specific position of the sequence obtained by performing 8:1 multiplexing processing.

9. The method according to claim 1, characterized in that, The value of N is 8 or 32; or The FEC codeword is an FEC internal codeword that has undergone external code FEC encoding and then internal code FEC encoding; or The FEC internal codeword is a Hamming codeword or a BCH codeword; or The data stream is a data stream received through the Attached Unit Interface (AUI); or The data stream is the data stream obtained by performing FEC decoding of the internal code.

10. The method according to any one of claims 1-9, characterized in that, The specific position corresponds to the starting position of the one or more convolutional interleaving sequences; or, The specific position corresponds to the starting position of the one or more distribution sequences; or, The specific position corresponds to the starting position of an integer multiple of the N data blocks; The starting position is the first bit, the first symbol, or the first byte.

11. The method according to any one of claims 1-10, characterized in that, The method further includes: Measure the first time delay corresponding to the data at each of the multiple specific locations to obtain multiple first delays; The target delay includes the maximum and / or minimum value among the plurality of first delays.

12. The method according to any one of claims 1-11, characterized in that, The target latency corresponding to data at multiple specific locations in the report data stream includes: Report the target latency corresponding to the data at the multiple specific locations in the data stream to the Media Access Control (MAC) layer.

13. A time delay reporting device, characterized in that, The apparatus is used to perform the method according to any one of claims 1 to 12.

14. A time delay reporting device, characterized in that, The device includes a circuit; The circuit is used to perform the method according to any one of claims 1 to 12.

15. The apparatus according to claim 14, wherein the apparatus comprises: Optical module, or physical PHY layer chip.

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