Automatic READ latency calculation without software intervention for a source-synchronous interface

Abstract

In response to a clock cycle and a pending READ command for data with a variably recurring access latency, a clock cycle count is adjusted. If a latency value has not been locked and if the READ command is a first READ command, the clock cycle count is stored as a locked latency value upon receiving a synchronized data available event (DQS for instance). Each subsequent READ command has an associated clock cycle count to enable pipelining wherein the clock cycle count for each READ starts incrementing when the individual READ command is issued. For subsequent READ commands, if the cycle count compares favorably with the locked latency value, data can be sampled safely from the interface at the identical latency for every READ request issued. The locked latency value can be read and / or written by software / hardware such that the read latency is consistent across multiple devices for reproducibility during debug.

Description

FIELD OF THE INVENTION[0001]The present invention relates to high-speed memory devices, and more particularly to read latency calculation in a high-speed memory device with variable recurring latency.BACKGROUND OF THE INVENTION[0002]The rapid increase in processor speed has necessitated a commensurate increase in memory access speed of off-chip caches or memory to prevent memory accesses from becoming a bottleneck. Traditionally, access to off-chip memory devices has been in accordance with a synchronous protocol. Synchronous protocols, in which off-chip accesses have a guaranteed bounded recurring latency relationship, have been easy to implement and are well defined. Synchronous protocols generally have been implemented by a clock that distributes a clock signal to an on-chip controller and to the off-chip caches or memory. Accesses are initialized and terminated only at transitions in value of the clock signal.[0003]However, interfaces for which synchronous protocols are used are...

AI Technical Summary

Problems solved by technology

However, interfaces for which synchronous protocols are used are limited by a physical delay between communicating devices.

System design requires a uniform clock among the various devices, mandating that clock wires be routed across the interface, increasing complexity of design.

Source-synchronous data transfers between devices in different timing domains can be complicated by latency, complexity, and a lack of repeatability.

This variance hampers debugging of a processor where cycle reproducibility is required.

The difficulty of debugging is further compounded when two processors with minor manufacturing differences are not comparable on a cycle-to-cycle basis.

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