The embodiment of the invention discloses a CDR (Clock Data Recovery) circuit and a terminal. The CDR circuit is used for carrying out clock synchronization in a terminal for achieving an EEE (Energy Efficient Ethernet) function; and the CDR circuit comprises a phase detector, a first phase signal selector, a loop filter, a numerically controlled oscillator, a second phase signal selector, a phase signal generator and a state machine. In the embodiment of the invention, after the terminal enters a refresh state from a quiesced state, the CDR circuit does not need to wait for the convergence of the loop filter and the numerically controlled oscillator to complete the clock synchronization with an opposite terminal, but a phase signal which meets preset clock synchronization conditions is generated by the phase signal generator and the second phase signal selector selects the phase signal which meets the preset clock synchronization conditions as a phase selected signal of CDR, so that the synchronization with the opposite terminal is rapidly implemented, the terminal can receive data sent by the opposite terminal when entering a normal working mode and the terminal can be ensured to achieve the EEE function.