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Latch structure, frequency divider, and methods for operating same

A latch and frequency divider technology, applied in pulse counters, synchronous pulse counters, counting chain pulse counters, etc., can solve problems such as limiting frequency selection

Active Publication Date: 2011-08-17
QUALCOMM INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This may unnecessarily limit the frequency choices available to designers of devices using odd frequency dividers

Method used

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  • Latch structure, frequency divider, and methods for operating same
  • Latch structure, frequency divider, and methods for operating same
  • Latch structure, frequency divider, and methods for operating same

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Embodiment Construction

[0017] In this document, the words "embodiment", "variation" and similar expressions are used to refer to a specific device, process or article, and not necessarily to the same device, process or article. Therefore, "one embodiment" (or similar expressions) used in one place or context may refer to a specific device, process or article; the same or similar expressions in different places may refer to different devices, processes or articles. The expressions "alternative embodiment", "alternatively" and similar phrases may be used to indicate one of many different possible embodiments. The number of possible embodiments is not necessarily limited to two or any other number.

[0018] The word "exemplary" may be used herein to mean "serving as an example, instance, or illustration." Any embodiment or variation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or variations. All embodiments and variations descr...

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Abstract

A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.

Description

[0001] Claim of priority under 35 U.S.C. §119 [0002] This patent application claims priority to U.S. Provisional Patent Application No. 61 / 098,665, filed September 19, 2008, entitled "LATCHSTRUCTURE AND FREQUENCY DIVIDER," which U.S. Provisional The patent application is assigned to the present assignee and is hereby expressly incorporated by reference in its entirety. technical field [0003] The present invention generally relates to electronic circuits and communication devices. More particularly, the disclosure relates, in several aspects, to latches, frequency dividers, synthesizers, and wireless communication devices using the same. Background technique [0004] Frequency dividers are used in a variety of electronic devices, including portable wireless devices such as cellular telephones and personal digital assistants. The output waveform of the frequency divider is usually derived from the rising or falling edge of the input of the frequency divider. To this en...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/356H03K5/156H03K23/54
CPCH03K5/1565H03K23/544H03K3/356121H03K3/356H03K5/156H03K23/54
Inventor 张昆肯尼思·巴尼特
Owner QUALCOMM INC
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