Clock frequency dividing method based on trigger ring and clock frequency dividing circuit thereof

Abstract

The present invention relates to a clock frequency division technology for an integrated circuit, in particular to a clock frequency division method based on a trigger ring and a clock frequency division circuit thereof. The method is to orderly connect data input ends and data output ends of a plurality of triggers to form a trigger ring circuit. The number of the triggers with set ends and reset ends in the trigger ring is selected according to the requirement of the frequency division circuit for a duty ratio. The positions of the triggers with set ends and reset ends are determined according to the requirement of a clock waveform. The trigger ring circuit accesses a system frequency division circuit, and a spare data output end of the last trigger is used as an output end of the trigger ring circuit so as to realize clock frequency division. The number of the frequency division of the method and the circuit structure thereof do not influence the highest frequency of the working circuit. The normal work of the frequency division circuit can be at a comparatively high clock frequency, and the clock frequency division can be realized in the manner of cascade connection of the frequency division circuit so that the scale of the circuit realization can be properly reduced.

Description

technical field [0001] The invention relates to a clock frequency dividing technology of an integrated circuit, in particular to a clock frequency dividing method based on a flip-flop ring and a clock frequency dividing circuit thereof. Background technique [0002] Clock frequency divider circuits are very common in the design of integrated circuits. Because the pad of the chip often cannot input a very high frequency clock, or there is no high frequency clock source outside the chip, a low frequency clock, such as 12M, is often input from the pad. The clock is connected to the input of the internal phase-locked loop. The phase-locked loop is a frequency multiplier circuit that can generate a high-frequency clock, such as a 480M clock, based on a lower-frequency input clock. Based on the consideration of function or power consumption, area and timing, one or more functional clocks (fclk1, fclk2, ....) are often needed inside the chip. The clock frequency dividing circuit is...

AI Technical Summary

Problems solved by technology

[0023] The delay of each level of combinational logic can be estimated, assuming it is 0.3ns, and the timing requirement of the flip-flop is 0.7ns. From this calculation, the delay of the whole circuit is 0.3×5+0.7=2.2ns, In other words, the highest frequency that such a circuit can work is 454MHz. If the clock frequency of the PLL is higher than 454MHz, the usual frequency division circuit will not work.

[0024] The usual solution to the above situation is to use two-stage frequency division, but the two-stage frequency division has the problem of inaccurate frequency division numbers, and it is inconvenient in timing analysis, and the multi-stage frequency division circuit sometimes has the defect of relatively large circuit scale

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