Relatively prime mode parallel counter based on congruence theory

Abstract

A relative prime modulo parallel counter based on the congruent theory relates to a counter of synchronous shift register type composed of a first, a second synchronous ring counters, and a decode unit, among which, the numbers of triggers in any two synchronous ring counters from the first to r are prime mutually, the clock pulse input ends of all synchronous ring counters are connected and linked to the clock pulse signals, the positive output or negative output end of each trigger in all said counters are connected to an input end of the decode unit. It uses the counter as its basic component and numbers of triggers in each are prime mutually, so a large count can be got with only a few ring counters.

Description

Technical field: [0001] The present invention relates to a synchronous shift register type counter. Background technique: [0002] With the rapid development of science and technology, modern society has put forward higher and higher requirements for high-speed precision measurement in the field of electronic testing. As the technical foundation of precise time measurement and frequency measurement, high-speed counting technology is a key research topic in the field of electronic measurement. A counter is a component that reflects state changes in a digital system, and the speed of change is a key parameter of the counter, which directly determines whether the counter is suitable for a certain digital system. There are many ways to classify counters. From whether the changes of each output bit are synchronous, they can be divided into synchronous counters and asynchronous counters. Synchronous counters are generally composed of flip-flops and logic gates. Gate delays and l...

AI Technical Summary

Problems solved by technology

However, since the order of the output state of this counter is not convenient to describe, and because this counter uses more hardware resources, it is rarely used in actual engineering applications

Synchronous counters with existing structures generally have the problem that as the number of flip-flops in the counter increases, the maximum counting frequency will inevitably decrease.

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