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Any input signal bit stream adder based on sigma-delta modulation

An input signal, delta modulation technology, which is used in calculations using digital representation, analog-to-digital converters, calculations using non-contact manufacturing equipment, etc. The effect of arithmetic precision

Inactive Publication Date: 2016-06-29
NANJING UNIV OF FINANCE & ECONOMICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] Therefore, all currently existing bit stream adders based on ΣΔ modulation cannot realize the addition of arbitrary input signals

Method used

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  • Any input signal bit stream adder based on sigma-delta modulation
  • Any input signal bit stream adder based on sigma-delta modulation
  • Any input signal bit stream adder based on sigma-delta modulation

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Embodiment Construction

[0038] In order to better understand the present invention, the content of the present invention is further illustrated below in conjunction with the examples, but the content of the present invention is not limited to the following examples.

[0039] like figure 2 The shown bit stream adder for any input signal based on sum delta modulation includes an n-input 1-bit binary adder, an enable terminal control logic unit, an n-bit ring counter group and an n+1-bit data selector; The output terminals of the n-input 1-bit binary adder are respectively connected to the enable terminal control logic unit and the n+1-bit data selector; the enable-end control logic unit, the n-bit ring counter group and the n+1-bit data selector connected in sequence.

[0040] In order to make the bit stream adder of any input signal produce the correct output result, an n-input 1-bit binary adder is used for n input signals x 1 、x 2 ,...,x n The instantaneous value is accumulated, and the accumul...

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Abstract

The invention discloses an any input signal bit stream adder based on sigma-delta modulation. The any input signal bit stream adder comprises a n input 1-bit binary adder, an enabling end control logic unit, a n-bit ring counter set and a n+1-bit data selector; the output end of the n input 1-bit binary adder is respectively connected with the enabling end control logic unit and the n+1-bit data selector; and the enabling end control logic unit, the n-bit ring counter set and the n+1-bit data selector are sequentially connected. According to the any input signal bit stream adder based on sigma-delta modulation disclosed by the invention, a n-bit code is used for representing an intermediate value required by a n input bit stream adder (n is an any value); the n-bit ring counter set is used for storing the intermediate value; corresponding ring counters are selected and driven under corresponding conditions to circularly output sequentially; the any input signal bit stream adder based on sigma-delta modulation is finally realized; and thus, the any input signal bit stream adder based on sigma-delta modulation has high operation precision.

Description

technical field [0001] The invention relates to a bit stream adder for arbitrary input signals based on sum delta modulation. Background technique [0002] The sum-delta analog-to-digital converter (ΣΔADC) is currently the highest precision ADC, capable of 24-bit precision. A ΣΔADC consists of a ΣΔ modulator and a downsampling filter. The ΣΔ modulator converts the analog signal into a 1-bit stream, and the downsampling filter converts the 1-bit stream into a conventional multi-bit digital signal. [0003] The 1-bit code stream output by the ΣΔ modulator is originally only the internal signal of the ΣΔADC. However, bit stream signal processing that has appeared in recent years directly processes this 1-bit code stream. The advantage is that each signal is transmitted by only one wire, and the structure of the bit stream signal processing unit is generally simpler than that of the multi-bit signal processing unit. Therefore, bit stream signal processing not only has the ad...

Claims

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Application Information

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IPC IPC(8): G06F7/50H03M1/12
Inventor 梁勇
Owner NANJING UNIV OF FINANCE & ECONOMICS
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