Sampling rate conversion filter and sampling rate conversion achieving method

Abstract

The invention discloses a sampling rate conversion filter and a sampling rate conversion achieving method. The filter comprises a filtering module used for conducting filtering processing on input signals, a first in first out (FIFO) module, a control module and a delay processing module. The FIFO module is used for writing signal data of each stage under control of the control module and conducting rate and clock domain conversion. The control module is used for controlling the delay processing module to read converted signal data of each stage and generating delay parameter. The delay processing module is used for reading converted signal data of each stage, adding the signal data of each stage and signal data of the previous stage subjected to position-cutting processing, multiplying the obtained sum with the delay parameter, conducting position-cutting processing on signal data obtained by multiplying and then transmitting the signal data to the next stage. Output signals are obtained till the last stage of signal data is processed. The filter reduces data processing amount through the position-cutting processing, reduces system resource occupation quantity, ensures time sequence through the FIFO unit and improves processing performance of the filter.

Description

technical field [0001] The invention relates to the technical field of signal processing, in particular to a sampling rate conversion filter and a sampling rate conversion realization method. Background technique [0002] In the prior art, when the fractional multiple sampling rate conversion of the signal is implemented, the sampling rate conversion filter of the Farrow structure is generally used for implementation. The structure of this filter is as figure 1 As shown, for the input signal x(k), each sub-filter C in the filtering part 1 L (z) filter, then input in the signal delay processing part 2; realize the fractional times delay of the signal in the signal delay processing part 2, wherein the signal delay processing part 2 adopts the structure of direct multiplication to realize the fractional times delay. The first subfilter C L After the output signal of (z) and the parameter ukv are multiplied by the multiplier, the obtained signal is combined with the second su...

AI Technical Summary

Problems solved by technology

[0004] The embodiment of the present invention provides a sampling rate conversion filter and a sampling rate conversion implementation method, which are used to solve the problems of resource waste and timing that cannot meet the conversion requirements when the existing filter implements decimal multiple sampling rate conversion.

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