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Signal processing device, signal processing method, delta-sigma modulation type fractional division PLL frequency synthesizer, radio communication device, delta-sigma modulation type D/A converter

A technology of a signal processing device and a frequency synthesizer, which is applied in the directions of analog-to-digital converters, physical parameter compensation/prevention, delta modulation, etc., can solve problems such as bad spurious signals, and achieve elimination of bad conditions, suppression of quantization noise, and elimination of quantization noise. The effect of spurious signals

Inactive Publication Date: 2005-02-23
PANASONIC CORP
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  • Claims
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AI Technical Summary

Problems solved by technology

[0006] Even the conventional ΔΣ modulation type D / A converter has the same spurious signal problem as the above-mentioned digital input relying on the ΔΣ modulator

Method used

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  • Signal processing device, signal processing method, delta-sigma modulation type fractional division PLL frequency synthesizer, radio communication device, delta-sigma modulation type D/A converter
  • Signal processing device, signal processing method, delta-sigma modulation type fractional division PLL frequency synthesizer, radio communication device, delta-sigma modulation type D/A converter
  • Signal processing device, signal processing method, delta-sigma modulation type fractional division PLL frequency synthesizer, radio communication device, delta-sigma modulation type D/A converter

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Embodiment Construction

[0017]

[0018] figure 1 It is a configuration block diagram of a mobile phone (wireless communication device) to which the ΔΣ modulation type fractional frequency division PLL frequency synthesizer of the present invention is applied. figure 1 The illustrated cellular phone has a ΔΣ modulation type fractional frequency division PLL frequency synthesizer 2, a frequency divider (DIV) 3, a modem (mixer) 4, a gain control amplifier (GCA) 5, a low pass filter (LPF ) 6, analog / digital (A / D) converter 7, digital / analog (D / A) converter 8, baseband LSI9, speaker 10, microphone 11, switch 12, antenna 13, low noise amplifier (LNA) 14 , Drive amplifier 15. f o Represents the output signal of the ΔΣ modulation type fractional frequency division PLL frequency synthesizer 2.

[0019]

[0020] figure 2 yes means figure 1 The block diagram of the internal structure of the ΔΣ modulation type fractional frequency division PLL frequency synthesizer 2 is shown. refer to figure 2 , Th...

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Abstract

A fractional frequency divider (28) includes a latch (31) for holding frequency division data, a DeltaSigma modulator (33), a digital dither circuit (32) for receiving a digital input F representing fraction part of the frequency division data from the latch (31) and supplying a digital output alternately changing between F+k and F-k (where k is an integer) or a F value itself to the DeltaSigma modulator (33), and circuit means (34 through 38) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the DeltaSigma modulator (33). The digital dither circuit (32) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the DeltaSigma modulator (33) receives a particular F value (e.g., F=2).

Description

technical field [0001] The invention relates to a signal processing device and a signal processing method, a ΔΣ modulation type fractional frequency division PLL frequency synthesizer, a wireless communication device, and a ΔΣ modulation type D / A converter. Background technique [0002] The ΔΣ modulator has a circuit structure that feeds back the quantization noise that appears in the output to the input side via a delay. It is either called a ΣΔ modulator, or it is called a called a noise shaper. [0003] When a frequency synthesizer composed of a phase-locked loop (PLL) is used in a wireless communication device such as a mobile phone, it is required to switch the output frequency in steps smaller than the reference signal frequency in order to secure a large usable frequency band. A ΔΣ modulation type fractional frequency division PLL frequency synthesizer is known as a device that can satisfy the above requirements, and one example thereof is shown in US Pat. No. 5,070,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/20H03L7/183H03L7/197H03M1/08H03M3/00H03M3/02H03M7/00H03M7/36H04B14/06
CPCH03M7/3042H03L7/1978H03M7/3008
Inventor 长曾洋一佐伯高晴
Owner PANASONIC CORP
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