Multibit single cell memory element having tapered contact

Abstract

An electrically operated, directly overwritable, multibit, single-cell chalcogenide memory element with multibit storage capabilities and having at least one contact for supplying electrical input signals to set the memory element to a selected resistance value, the second contact tapering to a peak adjacent to the memory element. In this manner the tapered contact helps define the size and position of a conduction path through the memory element.

Description

FIELD OF THE INVENTIONThe present invention relates generally to a uniquely designed solid state, electrically and optically operated, directly overwritable, low energy, very fast switching, non-volatile, analogue and multilevel single-cell operating memory element, and to high density electrical memory arrays fabricated from these elements. More specifically, the present invention relates to a memory element having a tapered contact layer.BACKGROUND AND PRIOR ARTThe Ovonic EEPROM is a novel, proprietary, high performance, non-volatile, thin-film electronic memory device. Its advantages include non-volatile storage of data, potential for high bit density and, consequently, low cost because of its small footprint and simple two-terminal device configuration, long reprogramming cycle life, low programming energies and high speed. The Ovonic EEPROM is capable of both analog and digital forms of information storage. Digital storage can be either binary (one bit per memory cell) or multi...

AI Technical Summary

Benefits of technology

There is disclosed herein an electrically operated, directly overwritable, multibit, single-cell memory element comprising a volume of memory material defining a single cell memory element, the memory material characterized by (1) a large dynamic range of electrical resistance values, and (2) the ability for at least a filamentary portion of the memory material to be set to one of a plurality of resistance values within the dynamic range in response to selected electrical input signals so as to provide the single-cell memory element with multibit storage capabilities. At least a filamentary portion of the single cell memory element being setable, by the selecte...

Problems solved by technology

This information is transferred, as needed, to faster and more expensive, but still non-volatile, hard disk memories.

Very fast computers even transfer forth and back small portions of the information stored in DRAM to even faster and even more expensive volatile static RAM (SRAM) devices so that the microprocessor will not be slowed down by the time required to fetch data from the relatively slower DRAM.

Transfer of information among the tiers of the memory hierarchy occupies some of the computer's power and this need for "overhead" reduces performance and results in additional complexity in the computer's architecture.

The electrically erasable phase change memories described in the Ovshinsky patents, as well as subsequent electrical solid state memory, had a number of limitations that prevented their widespread use as a direct and universal replacement for present computer memory applications, such as tape, floppy disks, magnetic or optical hard disk drives, solid state disk flash, DRAM, SRAM, and socket flash memory.

Specifically, the following represent the most significant of these limitations: (i) a relatively slow (by present standards) electrical switching speed, particularly when switched in the direction of greater local order (in the direction of increasing crystallization); (ii) a relatively high input energy requirement necessary to initiate a detectable change in local order; and (iii) a relatively high cost per megabyte of stored information (particularly in comparison to present hard disk drive media).

The most significant of these limitations is the relatively high energy input required to obtain detectable changes in the chemical and/or electronic bonding configurations of the chalcogenide material in order to initiate a detectable change in local order.

Such high energy levels translate into high current carrying requirements for the address lines and for the cell isolation/address device associated with each discrete memory element.

Taking into consideration these energy requirements, the choices of memory cell isolation elements for one skilled in the art would be limited to very large single crystal diode or transistor isolation devices, which would make the use of micron scale lithography and hence a high packing densit...

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