Processor system, as well as multi-channel memory copying DMA accelerator and method thereof

A technology of processor system and memory copy, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of slow copy speed, low system efficiency, lack of universal compatibility, etc., and achieve good portability, avoid dependence, and high The effect of parallelism

Active Publication Date: 2012-07-11
LOONGSON TECH CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] (1) Low system efficiency
The existing technology still needs the processor to execute relevant memory access and control instructions when performing memory copy, resulting in the processor being unable to perform other operations during the entire copy process, which is essentially a serial synchronous memory copy controlled by the processor
[0008] (2) Copy speed is slow
The processor in the prior art generally integrates 1-2 memory access components, and only after the current memory access instruction is c

Method used

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  • Processor system, as well as multi-channel memory copying DMA accelerator and method thereof
  • Processor system, as well as multi-channel memory copying DMA accelerator and method thereof
  • Processor system, as well as multi-channel memory copying DMA accelerator and method thereof

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Embodiment 1

[0064] Such as figure 2 As shown, the processor system of the embodiment of the present invention includes a processor core 1, a memory 3, and a multi-channel DMA (Direct Memory Access) connected between the processor core 1 and the memory 3 through a data bus Accelerator 4;

[0065] The multi-channel DMA accelerator 4 is used to judge and decompose the task information of the data read and write request according to the task information of the data read and write request when the processor core 1 sends the data read and write request of the memory copy command, and According to the task information of the decomposed data read-write request, and the read-write frequency and priority of multiple read-write channels, and the value of the flag bit of the read-write channel, control multiple read-write channels to send to the memory 3 in parallel Read and write requests multiple times to complete data reading and writing.

[0066] Preferably, as an implementable mode, the proce...

Embodiment 2

[0128] Correspondingly, an embodiment of the present invention provides a memory copy acceleration method, including the following steps:

[0129] Step S101, the control unit of the processor core sends a memory copy command to the multi-channel DMA accelerator;

[0130]Step S102, when the multi-channel DMA accelerator receives the data read and write request of the memory copy command sent by the processor core to the memory, it judges and decomposes the task information of the data read and write request according to the task information of the data read and write request, And according to the task information of the decomposed data read-write request, and the read-write frequency and priority of the multiple read-write channels, and the value of the flag bit of the read-write channel, control multiple read-write channels to issue to the memory in parallel Multiple read and write requests, parallel data read and write, until all read and write operations are completed;

[0...

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Abstract

The invention provides a processor system, as well as a multi-channel memory copying DMA (direct memory access) accelerator and a method thereof. The processor system comprises a multi-channel direct memory access (DMA) accelerator connected between a processor core and a memory through a data bus, and the multi-channel DMA accelerator is used for judging and decomposing task information of a data reading and writing request according to the task information of the data reading and writing request when the processor core emits the data reading and writing request of a memory copying command, controlling a plurality of reading and writing channels to emit the multiple reading and writing requests to the memory in parallel according to the task information of the data reading and writing request after decomposition, the reading and writing frequencies and the priorities of the plurality of the reading and writing channels in the task information and values of marker bits of the reading and writing channels, and further completing data reading and writing. The processor system has the advantages of high bandwidth, low latency, high degree of parallelism, reconfigurability and platform independence.

Description

technical field [0001] The present invention relates to the technical field of computer hardware architecture and processor design, in particular to a processor system based on processor embedded multi-channel direct memory access (Direct Memory Access, DMA) that supports asynchronous memory access and parallel memory read and write. Its multi-channel memory copy DMA accelerator and method. Background technique [0002] In existing computer systems, memory copy (Memory Copy) is an important operation for transferring data between different locations in memory. It widely exists in operating systems and various application programs. Relevant studies have found that memory copy operations can account for 20%-40% of the total time overhead in TCP / IP protocol processing. In the operating system, the memory copy operation realizes its function through the standard system functions memcpy and bcopy defined by the system kernel. For different computer architectures, the specific i...

Claims

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Application Information

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IPC IPC(8): G06F13/28
Inventor 苏文苏孟豪
Owner LOONGSON TECH CORP
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