Method for realizing instruction buffer lock

An implementation method and instruction caching technology, which is applied in concurrent instruction execution, memory system, memory address/allocation/relocation, etc., can solve the problems of data cache locks not evaluating the cost-effectiveness, performance improvement, and large performance loss. Achieve the effect of reducing memory access delay, improving performance and energy saving, and high accuracy

Inactive Publication Date: 2011-03-23
ZHEJIANG UNIV
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

There are also some cache lock methods that have a loop structure, and each loop needs to be evaluated and predicted. The performance loss is large, and the same method is used to evaluate the price/performance ratio, which leads to inaccur

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  • Method for realizing instruction buffer lock
  • Method for realizing instruction buffer lock
  • Method for realizing instruction buffer lock

Examples

Experimental program
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Embodiment

[0046] There is a program A. The memory block access sequence during the running of the program is (m0m1m2m3m4m5m6m7)10. This sequence is accessed 10 times. Each block is mapped to the same cache group, and the cache is 4-way associative. In the case of no lock, all of this access sequence will miss, that is, all 80 accesses will be lost. According to the instruction cache lock technology, if any 4 of these 8 memory blocks, such as m0, m1, m2, and m3, are locked In the instruction cache, the misses are reduced by half. This process is very simple. The most important thing is to store the program memory block access information and the lock status strategy of each block on the peripheral.

[0047] In this example, after the access of m0-m7, the access counter value of each block is 0, it is difficult to distinguish which block is better to lock, but the LRU count value is different, the value of m4m5m6m7 is relatively low, which is 3, respectively. 2, 1, 0, then you can consid...

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Abstract

The invention discloses a method for realizing instruction buffer lock, which comprises the following steps: 1) analyzing program summary, pre-running a section of program, and recording a memory block access sequence, citation times, re-access time interval and hit times; and 2) selecting memory blocks to be locked in a buffer, setting an access counter and a least recently used (LRU) counter for each memory block, accessing memory block access times recorded in the counters, assigning weights N1 and N2 to the access counter and LRU counter in each memory block, counting according to N1*access times+N2*(LRU counter limit-LRU value), and if the counted values are greater than a threshold M, locking the memory blocks in the buffer, wherein N1+N2=1. In the invention, the memory blocks locked in the instruction buffer can be replaced only when the lock is removed, the buffer hit rate is improved greatly, the accesses to low-level storage are reduced, and average memory access delay is reduced.

Description

technical field [0001] The invention relates to the storage field in the architecture, in particular to a method for realizing an instruction cache lock. Background technique [0002] At present, the performance of most embedded systems is determined by the average memory access delay to a large extent. Improving the cache hit rate can reduce the number of memory accesses and improve system performance. Some current embedded processors use a cache lock mechanism to lock some memory blocks in the cache under software control. The role of the cache is mainly to alleviate the speed and performance mismatch between the adjustment processor and the low-speed main memory. In the actual process, the instruction cache plays a vital role in the performance and energy consumption of the embedded system, because the instruction is is fetched every clock cycle. The improvement of instruction cache performance has a great impact on the overall system performance, and many technologies ...

Claims

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Application Information

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IPC IPC(8): G06F12/08G06F9/38G06F12/0875
Inventor 陈天洲虞保忠乐金明马建良乔福明
Owner ZHEJIANG UNIV
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